Clocking and timing IP cores are fundamental to semiconductor designs that require accurate clock generation, distribution, synchronization, and timing control. This category includes PLLs, DLLs, oscillators, and clock generators used in SoCs, ASICs, SerDes subsystems, processors, memory interfaces, and communication devices.
Browse clocking and timing IP from multiple vendors to compare jitter, frequency range, locking behavior, power consumption, programmability, and process support. Semi IP Hub helps chip architects and design engineers identify the right timing IP for high-performance and low-power silicon platforms.
HDMI 2.1 Audio PLL in TSMC (16nm, 12nm)
The Synopsys HDMI 2.1 RX Controller and PHY IP solutions, compliant with the High-Definition Multimedia Interface (HDMI) 2.1 spec…
HDMI 2.1 Audio PLL in Samsung (14nm)
The Synopsys HDMI 2.1 RX Controller and PHY IP solutions, compliant with the High-Definition Multimedia Interface (HDMI) 2.1 spec…
5GHz to 13.5GHz PLL - TSMC 130nm
The PLL13G is an ultra-low power phase locked loop (PLL) intellectual property (IP) block.
200 MHz—800 Mhz PLL - X-Fab 180nm CMOS
The PLL800M is a ultra-low power phase locked loop (PLL) intellectual property (IP) block.
Low-power 32 kHz RC oscillator in GF 22FDX+
OSC-RC-32k-A03-D18-GF22P.01_GF_22_FDX+ is a 32 kHz RC oscillator in GF 22FDX+ based on a low-power architecture for the implement…
5 GHz 250 fs Jitter PLL - GlobalFoundries 22nm
The PLL5G250F is an ultra-low power phase locked loop (PLL) intellectual property (IP) block.
6GHz-12.5GHz PLL in GF 22nm FDX
Ultra-low jitter, low-power ring-oscillator-based PLL- 6GHz-12.5GHz in GF 22nm FDX
UCIe based 8-bit 48-Gsps Transceiver (ADC/DAC/PLL/UCIe)
Unleash the power of the new UCIe based RF Chiplet transceiver.
UCIe based 12-bit 12-Gsps Transceiver (ADC/DAC/PLL/UCIe)
Unleash the power of the new UCIe based RF Chiplet transceiver.
The high performance PLL is a high speed, low jitter frequency synthesizer, developed as an IP block to reduce time to market, ri…
8-bit 48-Gsps Transceiver (ADC/DAC/DLL)
Unleash the power of precision and innovation with the NS_TRX_48G_G12, a 8-bit, 48-Gsps Transceiver with embedded ADC, DAC, 8X cl…
12-bit 12-Gsps Transceiver (ADC/DAC/PLL)
Unleash the power of precision and innovation with the NS_TRX_12G_T16, a 12-bit, 12-Gsps Transceiver with embedded ADC, DAC, PLL,…
Aeonic Generate Clock Generation Module [PLL], 8x smaller than fractional analog solutions
The Movellus™ high-performance Aeonic Generate Clock Generation Module (CGM) is a high-quality clock synthesis IP that is part of…
Active frequency doubler, designed for use in the LO Path after VCO to double up the LO frequency
RFDBL03C is an active frequency doubler, designed for use in the LO Path after VCO to double up the LO frequency within the IC to…
Low jitter 4.96GHz to 5.6GHz PLL in TSMC N40
PMCC_PLL5GN40 is a PLL IP block which synthesizes low-jitter (
32KHz XTAL oscillator specifically designed for ultra low power applications.
Ultra-Low Power Fractional-N digital PLL for IoT Applications in 40nm CMOS
IMEC’s divider-less All-Digital Phase Locked Loop (ADPLL) combines world’s lowest power consumption with performance and small si…
SGC21549_IP007702_GF_22FDX is a digitally controlled RC based oscillator with embedded Physically Unclonable Function (PUF) imple…
Low Jitter Digital PLL – 1.25G/2.5G/5G
The Multiband Quadrature frequency synthesizer generates three frequencies 1.25G / 2.5G / 5G.
040TSMC_OSC_01 is a CMOS inverter of a Pierce-type variation with an integrated Temperature Compensated Crystal (Xtal) Oscillator…