AMBA LPI Assertion IP
AMBA LPI Assertion IP provides an efficient and smart way to verify the AMBA LPI designs quickly without a testbench.
Overview
AMBA LPI Assertion IP provides an efficient and smart way to verify the AMBA LPI designs quickly without a testbench. The SmartDV's AMBA LPI Assertion IP is fully compliant with standard AMBA LPI Specification.
AMBA LPI Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
AMBA LPI Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
Key features
- Specification Compliance
- Compliant to ARM AMBA LPI protocol
- Supports LPI Q-Channel and P-Channel signal level checks
- Assertion IP features
- Assertion IP includes:
- System Verilog assertions
- System Verilog assumptions
- System Verilog cover properties
- Synthesizable Verilog Auxiliary code
- Support Master mode, Slave mode, Monitor mode and Constraint mode.
- Supports Simulation mode (stimulus from SmartDV LPI VIP) and Formal mode (stimulus from Formal tool).
- Rich set of parameters to configure LPI Assertion IP functionality.
Block Diagram
Benefits
- Runs in every major formal and simulation environment.
What’s Included?
- Detailed documentation of Assertion IP usage.
- Documentation also contains User's Guide and Release notes.
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
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Frequently asked questions about Protocol Bridge IP cores
What is AMBA LPI Assertion IP?
AMBA LPI Assertion IP is a Protocol Bridge IP core from SmartDV Technologies listed on Semi IP Hub.
How should engineers evaluate this Protocol Bridge?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Protocol Bridge IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.