Vendor: SmartDV Technologies Category: Protocol Bridge

AMBA AXI5-Lite Synthesizable Transactor

AMBA AXI5-Lite Synthesizable Transactor provides a smart way to verify the ARM AMBA AXI5-Lite component of a SOC or a ASIC in Emu…

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Overview

AMBA AXI5-Lite Synthesizable Transactor provides a smart way to verify the ARM AMBA AXI5-Lite component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's AMBAAXI5-Lite Synthesizable Transactor is fully compliant with standard AMBA AXI5-Lite Specification and provides the following features

Key features

  • Compliant with the latest ARM AXI5-Lite Protocol Specification.
  • Supports AXI5-Lite Master and Slave.
  • Supports all AXI5-Lite data and address widths.
  • Supports all protocol transfer types, burst types, burst lengths, burst sizes and response types.
  • Supports constrained randomization of protocol attributes.
  • Separate address, data and response phases. Separate read and write channels.
  • Support for burst-based transactions with only start address issued.
  • Slave supports fine grain control of response per address or per transaction.
  • Programmable wait states or delay insertion on different channels.
  • Ability to inject errors during data transfer.
  • Write strobe support to enable sparse data transfer on the write data bus.
  • Narrow transfer support.
  • Unaligned address access support.
  • Protected accesses with normal/privileged, secure/non-secure and data/instruction
  • Ability to configure the width of all signals.
  • Support for bus inactivity detection and timeout.
  • Configurable WID signal enable support.
  • Quality of Service signaling.
  • Multiple region interfaces.
  • User signaling support.
  • Supports unmapped region address accesses
  • AWCACHE and ARCACHE Attributes.
  • Low-power Interface support
  • Write strobe support.
  • AXI5-Lite specific features
    • All transactions burst length 1.
    • Reordering of responses for requests with different IDs.
    • All accesses Device Non-bufferable.
    • Atomic access support with normal access.
  • Programmable Timeout insertion.
  • Rich set of configuration parameters to control AXI5-Lite functionality.
  • On-the-fly protocol and data checking.
  • Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
  • Callbacks in Master and Slave for various events.
  • Status counters for various events on bus.

Block Diagram

AMBA AXI5-Lite Transactor block diagram

Benefits

  • Compatible with testbench writing using SmartDV VIP's
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms

What’s Included?

  • Synthesizable transactors
  • Complete regression suite containing all the AMBA AXI5-Lite Synthesizable testcases
  • Examples showing how to connect various components, and usage of Synthesizable Transactor
  • Detailed documentation of all class, task and functions used in verification env
  • Documentation contains User's Guide and Release notes

Specifications

Identity

Part Number
AMBA AXI5-Lite Transactor
Vendor
SmartDV Technologies
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact SmartDV Technologies

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Frequently asked questions about Protocol Bridge IP cores

What is AMBA AXI5-Lite Synthesizable Transactor?

AMBA AXI5-Lite Synthesizable Transactor is a Protocol Bridge IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this Protocol Bridge?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Protocol Bridge IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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