Vendor: SmartDV Technologies Category: Protocol Bridge

AMBA AXI4-Stream Synthesizable Transactor

AMBA AXI4 Stream Synthesizable Transactor provides a smart way to verify the ARM AMBA AXI4-Stream component of a SOC or a ASIC in…

Contact Provider Request Datasheet

Overview

AMBA AXI4 Stream Synthesizable Transactor provides a smart way to verify the ARM AMBA AXI4-Stream component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's AMBA AXI4-Stream Synthesizable Transactor is fully compliant with standard AMBA AXI4 Stream Specification and provides the following features

Key features

  • Compliant with the latest ARM AMBA AXI4-Stream Protocol Specification.
  • Supports AXI4-Stream Master and Slave.
  • Supports all AXI4-Stream data widths.
  • Support for all Data streams including Byte stream, Continuous aligned stream,Continuous unaligned stream and Sparse stream.
  • Support for single byte, packet and frame transfers.
  • Transfer interleaving support.
  • Support for upsizing, downsizing and merging.
  • Supports constrained randomization of protocol attributes.
  • Slave supports fine grain control of response.
  • Programmable wait states or delay insertion.
  • Ability to inject errors during transfer.
  • Ability to configure the width of all signals.
  • Support for bus inactivity detection and timeout.
  • Programmable Timeout insertion.
  • Rich set of configuration parameters to control AXI4-Stream functionality.
  • On-the-fly protocol and data checking.
  • Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
  • Callbacks in Master and Slave for various events.
  • Status counters for various events on bus

Block Diagram

AMBA AXI4-Stream Transactor block diagram

Benefits

  • Compatible with testbench writing using SmartDV VIP's
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms

What’s Included?

  • Synthesizable transactors
  • Complete regression suite containing all the AMBA AXI4-Stream Synthesizable Transactor testcases
  • Examples showing how to connect various components, and usage of Synthesizable Transactor
  • Detailed documentation of all class, task and functions used in verification env
  • Documentation contains User's Guide and Release notes

Specifications

Identity

Part Number
AMBA AXI4-Stream Transactor
Vendor
SmartDV Technologies
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact SmartDV Technologies

Learn more about Protocol Bridge IP core

A comparison of Network-on-Chip and Busses

This whitepaper summarizes the limitations of traditional bus-based approaches, introduces the advantages of the generic concept of NoC, and provides specific data about Arteris’ NoC, the first commercial implementation of such architectures

IP Core for an H.264 Decoder SoC

This paper presents the development of an IP core for an H.264 decoder. This state-of-the-art video compression standard contributes to reduce the huge demand for bandwidth and storage of multimedia applications. The IP is CoreConnect compliant and implements the modules with high performance constraints.

Frequently asked questions about Protocol Bridge IP cores

What is AMBA AXI4-Stream Synthesizable Transactor?

AMBA AXI4-Stream Synthesizable Transactor is a Protocol Bridge IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this Protocol Bridge?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Protocol Bridge IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP