Two Dollars and a Test Suite
The Arm-Qualcomm verdict made headlines for its $2 award. The finding that matters more is about who controls the compliance tests a custom chip must pass before it can ship.
Vendor:
Veriest Solutions Ltd.
Category:
Protocol Bridge
AMBA AXI Data Prefetch Buffer
The Veriest AMBA AXI Data Prefetch Buffer Design IP provides a mechanism read / prefetch contiguous data over the AXI from a memo…
Overview
The Veriest AMBA AXI Data Prefetch Buffer Design IP provides a mechanism read / prefetch contiguous data over the AXI from a memory such as DDR SDRAM in which the data may need to be available immediately. The prefetched data is stored in a FIFO. The parameters for the source addresses are configured by way of the APB bus.
Key features
- Easy integraton
- AMBA AXI 3.0 Compatible
- Configurable FIFO depth
- Programmable source address parameters
- Automatic address calculation
- Output data FIFO with configurable depth
- Data input width 128-bit
- AXI input data width 128-bit
- APB interface for configuration and status
- Software reset
- Configurable AXI bursts
- Event Interrupt Indication
Block Diagram
VV2010 block diagram
Benefits
- Low Gate Count
- Low Power Consumption
- Spyglass Lint Validated
- Standards Compliant
Applications
- General System on Chip Use
What’s Included?
- Synthesizable Verilog RTL
- Detailed block diagram and technical documents
Specifications
Identity
Part Number
VV2010
Vendor
Veriest Solutions Ltd.
Type
Silicon IP
Provider
HQ:
Israel
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Frequently asked questions about Protocol Bridge IP cores
What is AMBA AXI Data Prefetch Buffer?
AMBA AXI Data Prefetch Buffer is a Protocol Bridge IP core from Veriest Solutions Ltd. listed on Semi IP Hub.
How should engineers evaluate this Protocol Bridge?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Protocol Bridge IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.