Vendor: Veriest Solutions Ltd. Category: Protocol Bridge

AMBA AHB Address Trapper

The Veriest AMBA AHB Address Trapper Design IP provides a mechanism for debug of an AMBA AHB bus.

Overview

The Veriest AMBA AHB Address Trapper Design IP provides a mechanism for debug of an AMBA AHB bus. This gives added visibility to the software in order to debug address related issues in an SoC in simulation or on a fabricated chip. In the event of an address that does not decode to a defined slave, the access should be redirected towards an instance of the Address Trapper by the AHB decoder in the AHB bus controller. The faulty address and master number is captured and stored in a FIFO of configurable depth. The FIFO contents can be read out by the CPU over the APB interface. The CPU can receive an interrupt event to indicate that the FIFO contains debug information.


Key features

  • Easy integraton
  • AMBA AHB 3.0 Compatible
  • Configurable FIFO depth
  • Event Interrupt Indication

Block Diagram

VV1900 block diagram

Benefits

  • Low Gate Count
  • Low Power Consumption
  • Spyglass Lint Validated
  • Standards Compliant

Applications

  • General System on Chip Use

What’s Included?

  • Synthesizable Verilog RTL
  • Detailed block diagram and technical documents

Specifications

Identity

Part Number
VV1900
Vendor
Veriest Solutions Ltd.
Type
Silicon IP

Provider

Learn more about Protocol Bridge IP core

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Frequently asked questions about Protocol Bridge IP cores

What is AMBA AHB Address Trapper?

AMBA AHB Address Trapper is a Protocol Bridge IP core from Veriest Solutions Ltd. listed on Semi IP Hub.

How should engineers evaluate this Protocol Bridge?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Protocol Bridge IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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