Vendor: EnSilica Category: Analog Front End

AGC Control and data plane core

The eSi-AGC core provides the control and data plane interfaces to an AGC module.

Overview

The eSi-AGC core provides the control and data plane interfaces to an AGC module. The signal processing in the core consists of a sliding energy estimate and saturation detection.

Key features

  • Sliding window energy estimator on IQ input samples
  • Decibel conversion
  • Clipping detection with median filter
  • Configurable setpoint
  • Configurable hysteresis to avoid hunting around the setpoint
  • Configurable fast AGC descent on detecting regular clipping
  • •un-time control of latency for input data following a change in AGC value
  • AXI4-Streaming inputs and outputs
  • APB configuration
  • Verilog 2001

Benefits

  • Simple standard interfacing
  • Low-gate count

Applications

  • Multi-standard wireless receivers
  • Software defined radios (SDR) accelerator
  • OFDM synchronization

What’s Included?

  • RTL
  • Testbench
  • Synthesis scripts
  • Documentation
  • MATLAB and C++ bit exact model

Specifications

Identity

Part Number
eSi-AGC
Vendor
EnSilica
Type
Silicon IP

Provider

EnSilica
HQ: UK

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Frequently asked questions about Analog Front End IP cores

What is AGC Control and data plane core?

AGC Control and data plane core is a Analog Front End IP core from EnSilica listed on Semi IP Hub.

How should engineers evaluate this Analog Front End?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Analog Front End IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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