Vendor: Algotronix Ltd. Category: Symmetric Crypto

AES Core G2

The G2 AES encryption core represents the second generation of Algotronix' AES technology: it is a stable, NIST validated impleme…

AES View all specifications

Overview

The G2 AES encryption core represents the second generation of Algotronix' AES technology: it is a stable, NIST validated implementation of the entire algorithm as specified in NIST publications FIPS197 and SP800-38A and includes an implementation of the entire NIST AESAVS test suite.

Algotronix can also provide a design service to extend or tailor the core to meet the specific requirements of your application.

Key features

  • Fully synchronous with single clock and enable
  • Configurable via VHDL generic parameters to trade features and performance against area
  • Source code available for security review
  • Cost Effective Royalty Free licencing with a variety of options to suit project requirements

Benefits

  • Easy to use, single clock and enable
  • Enable allows pausing the core on a cycle by cycle basis for flow control

Applications

  • The 32 bit data path used in this core is suitable for securing low to medium speed communications - up to 500Mbit/sec depending on the target FPGA. For 500Mbit to 3Gbit applications our G3 core with a 128 bit datapath can be used and for 3 - 100Gbits one of our pipelined cores is required.

What’s Included?

  • VHDL source code
  • FPGA vendor tool project directories
  • Processor Interface application note
  • Getting Started reference design for FPGA vendor evaluation boards

Specifications

Identity

Part Number
AES-G2
Vendor
Algotronix Ltd.
Type
Silicon IP

Security

Crypto Algorithm
AES

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Algotronix Ltd.
HQ: United Kingdom

Learn more about Symmetric Crypto IP core

Algotronix provides AES encryption over USB with new reference designs

Algotronix has announced the availability of a reference design that provides Advanced Encryption Standard (AES) over USB. The company provides an interface to Altera's NIOS II soft processor that works with their G3 core to provide AES encryption and decryption of files passed over a USB 2 interface.

How to defend against the cloning of your FPGA designs

This article describes a new way of tagging designs to help to counter the rapidly growing trade in stolen IP and cloned designs. The topic is a difficult one for the industry to discuss; recently, however, more and more voices have been raised on the issue.

Frequently asked questions about Symmetric Cryptography IP cores

What is AES Core G2?

AES Core G2 is a Symmetric Crypto IP core from Algotronix Ltd. listed on Semi IP Hub.

How should engineers evaluate this Symmetric Crypto?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Symmetric Crypto IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP