Vendor: Crucial IP Inc. Category: Video Processing

Adaptive Detail Enhancer

The VPC-5 is a 2D adaptive detail enhancer which selectively enhances the appearance of edges and textures without enhancing the …

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Overview

The VPC-5 is a 2D adaptive detail enhancer which selectively enhances the appearance of edges and textures without enhancing the appearance of noise. Separate controls are provided for both edge and texture enhancement as well as for the amount of enhancement to be applied in each dimension. A programmable threshold for discriminating textures from noise is also provided. Careful algorithm design and piecewise linear control ensure a well behaved response without large changes at the output in response to small changes at the input. Programmable overshoot clamping is provided to limit the amount of overshoot associated with enhancement. The VPC-5 Adaptive Detail Enhancer can be combined with the VPC-3 Mosquito/Block Noise Reducer to provide a complete suite of enhancement and noise reduction tools.

The VPC-5 is available with complete Verilog source code, Verilog test bench and bit-accurate C model as part of the license. Integration and programming guidelines are also included backed up by expert technical support.

A VPC-5 reference design is available for standard development kits from Xilinx and Altera for demonstration and evaluation purposes. The design includes a built-in user interface with embedded OSD to simplify access to key features of the IP. In addition to simplifying the evaluation of the VPC-5 IP core, the design also serves as a template for customer application development.

Key features

  • General
    • The following input formats are supported: 480p, 576p, 720p, 1080p and other custom formats (function should be located downstream from deinterlacer)
    • 8/10/12-bit 4:2:2 or 4:4:4 processing
    • Low latency (~2 lines)
    • Fully synchronous design
  • Enhancement
    • Selectively enhances sharpness of edges and textures
    • Separate controls provided for edge and texture enhancement
    • Enhances edges and textures without amplifying noise
    • Programmable threshold for discriminating textures from noise
    • Enhancement applied in both horizontal and vertical dimensions with separate level controls provided
    • Programmable overshoot clamping control
  • Compatibility
    • Use standalone or in conjunction with other Crucial IP cores or third party IP
    • Support for both Xilinx and Altera devices

What’s Included?

  • Synthesizable Verilog RTL source code (encrypted or unencrypted as per license agreement)
  • Verilog testbench
  • Bit-accurate C model
  • Verification test suite
  • Product documentation
  • Integration guidelines
  • Integration support

Specifications

Identity

Part Number
VPC-5
Vendor
Crucial IP Inc.
Type
Silicon IP

Files

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Provider

Crucial IP Inc.
HQ: Canada
Based in Toronto, Crucial IP Inc. is a provider of silicon IP and design services to the Consumer Electronics and Broadcast industries. Founded by a team of veterans with over 50 years of combined experience in consumer video and computer graphics, Crucial IP is committed to providing high quality, cost effective IP cores for ASIC and FPGA implementation. With a focus on image quality and robust design, all cores have been subjected to hundreds of hours of rigorous testing. As silicon densities continue to increase, competitive pressures dictate that companies incorporate more and more functionality into their designs, whether implemented in the ASIC or FPGA domain. Eventually, companies must reach beyond their core competencies into areas less familiar to them. The popularity of IP cores such as microprocessors and interface blocks including USB, showcases this fact. The use of 3rd party IP and design services allows companies to bring the required functionality to market in a low risk and cost effective manner. Crucial's silicon IP cores are available for licensing at the source code level providing customers with maximum flexibility and future-proofing. For customers with particular needs, Crucial IP can offer optional customization services in addition to the included technical support. As well as standard and customized IP products, full custom design services are also available. All of Crucial IP's video cores are available for evaluation using an FPGA platform.
Contact Crucial IP Inc.

Learn more about Video Processing IP core

Picking the right MPSoC-based video architecture: Part 1

A look at the design of multiprocessor systems-on-chips (MPSoCs) for video applications and how to optimize them for computational power and real-time performance as well as flexibility. Part 1: Architectural approaches to video processing

Analysis: ARC's Configurable Video Subsystems

Adding to its growing portfolio of licensable silicon IP subsystems, ARC has announced five configurable video processing subsystems. The subsystems range from the smallest-size AV 402V to the highest-performance AV 417V, and support multi-standard video encoding and decoding at resolutions ranging from CIF to D1.

Frequently asked questions about Video Processing IP

What is Adaptive Detail Enhancer?

Adaptive Detail Enhancer is a Video Processing IP core from Crucial IP Inc. listed on Semi IP Hub.

How should engineers evaluate this Video Processing?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Video Processing IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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