Vendor: Weasic Microelectronics Category: PLL

8.3 GHz to 10.9 GHz Low phase Noise Fractional-N Synthesizer

The WEA811S45G is a wide band fractional –N frequency synthesizer with the integrated VCOs implemented in the GlobalFoundries 45R…

Overview

The WEA811S45G is a wide band fractional –N frequency synthesizer with the integrated VCOs implemented in the GlobalFoundries 45RFSOI process. It uses a reference input ranging from 25 MHz to 300 MHz, with the use of a XTAL buffer / XTAL Oscillator. The WEA811S45Gcan generate an RF signal ranging from 8.3 GHz up to 10.9 GHz frequency range with a bank of 3 integrated VCOs. The synthesizer has the ability to automatically lock into the selected frequency utilizing an algorithm that selects linearly between the various VCOs and binary weights between the 128 bands. The WEA811S45G is powered by 1.8 V supply.

Key features

  • Low phase Noise PLL
  • 1.8 V Supply Voltages
  • RF frequency range: 8.3 GHz to 10.9 GHz
  • Reference input 25 – 300 MHz
  • RF Fractional-N synthesizer
  • GDS ready
  • Area: 1000 um x 1800 um

Block Diagram

Applications

  • Communications

Specifications

Identity

Part Number
WEA811S45G
Vendor
Weasic Microelectronics
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

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Frequently asked questions about PLL IP cores

What is 8.3 GHz to 10.9 GHz Low phase Noise Fractional-N Synthesizer?

8.3 GHz to 10.9 GHz Low phase Noise Fractional-N Synthesizer is a PLL IP core from Weasic Microelectronics listed on Semi IP Hub.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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