Vendor: nSilition Category: PLL

62.5MHz to 2GHz low jitter 1.2V supply PLL

The nSPLL_SIL130G_1V2 cell is a fully-programmable PLL IP cell powered at 1.2V ±10% designed on the Silterra 130 G technology.

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Overview

The nSPLL_SIL130G_1V2 cell is a fully-programmable PLL IP cell powered at 1.2V ±10% designed on the Silterra 130 G technology. Its input reference frequency can be chosen between 1 and 250MHz and the output between 62.5MHz and 2GHz.

Key features

  • Type II, 3rd order low jitter PLL
  • Single 1.2V +/-10% power supply
  • 62.5MHz - 2GHz programmable output frequency (D = 1-16)
  • Programmable serialization factor (N = 1-10)
  • Programmable charge-pump frequency (P = 1-16)
  • PLL jitter spectrum optimization
  • -40 to +125C junction temperature
  • Standby/power down mode
  • Low silicon surface

Block Diagram

nSPLL_SIL130G_1V2 block diagram

Benefits

  • Silterra 130 G
  • 1.2V +/-10% power supply
  • -40 to +125C

Applications

  • Clock multiplication
  • Clock recovery
  • High-speed generator for Ser/Des PHYs

What’s Included?

  • GDS II layouts
  • LEF abstracts
  • CDL netlists
  • Liberty timings
  • Verilog description
  • A full datasheet
  • An integration note

Specifications

Identity

Part Number
nSPLL_SIL130G_1V2
Vendor
nSilition
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

nSilition
HQ: Belgium
Contact nSilition

Learn more about PLL IP core

Creating a Frequency Plan for a System using a PLL

How do you ensure that every part of a system receives the clock it needs—without wasting power or sacrificing performance? The answer lies in creating a well-structured frequency plan built around a PLL.

Specifying a PLL Part 3: Jitter Budgeting for Synthesis

This white paper is aimed at system architects and physical implementation leaders working on the design of SoCs. It can be confusing to understand the impact of different jitter sources and how to calculate a jitter budget when specifying a digital system. This white paper explains how jitter changes the period of a clock and how to ensure that jitter has correctly been accounted for in the calculations for timing closure.

Specifying a PLL Part 2: Jitter Basics

This article explains a some of the key terminology and parameters commonly used to describe jitter. It will also help clarify the most important parameters for a some PLL applications, allowing the designer to better understand what is required from a PLL.

Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR

In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.

Achieving Groundbreaking Performance with a Digital PLL

This article compares analog, first-generation digital, and second-generation digital PLLs. It evaluates which type of PLL may be best in which situation. It further discloses a roadmap into other application areas, including general purpose / logic clocking, and regular low-jitter PLLs.

Frequently asked questions about PLL IP cores

What is 62.5MHz to 2GHz low jitter 1.2V supply PLL?

62.5MHz to 2GHz low jitter 1.2V supply PLL is a PLL IP core from nSilition listed on Semi IP Hub.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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