Vendor: Global UniChip Corp. (GUC) Category: DAC

40nm LP 2.5V/1.1V 12bit 80Mhz Current Steering DAC [2ch]

The IGADACS02A is a general-purpose two-channel digital-to-analog converter with 12-bit resolution.

12 Bit TSMC 40nm LP Silicon Proven View all specifications

Overview

The IGADACS02A is a general-purpose two-channel digital-to-analog converter with
12-bit resolution. The sampling rate is up to 80M samples per second. The IGADACS02A
contains two current steering DAC circuits and two current-to-voltage buffers. Both current
output and voltage output modes are available. The input data format can be either
unsigned binary or 2’s complement.
This DAC need one external reference resistor for current reference. 2.5V devices are
used for analog and high-voltage logic circuits; 1.1V devices are used for core-voltage logic
circuits. A power down mode is available to disable the DAC and lower down the power
consumption.
The IGADACS02A is fabricated in TSMC 40nm 2.5V/1.1V logic low power CMOS
process with 1P6M & 1P7M layout.

Key features

  • 40nm 2.5V/1.1V logic low power CMOS process with 1P6M & 1P7M layout ( 4X1Z, 4X1U, & 5X1Z )
  • 12-bit resolution with maximum 80MHz conversion rate
  • Both current output and voltage output modes are available
  • 1.28Vpp compliance range for current output mode
  • Operation temperature range: -40°C ~ 85°C
  • DNL < +/- 1LSB, INL < +/- 1.5LSB, No missing code
  • Adjustable full scale current
  • Power down mode is available
  • Area = 0.28 mm2

Silicon Options

Foundry Node Process Maturity
TSMC 40nm LP Silicon Proven

Specifications

Identity

Part Number
IGADACS02A
Vendor
Global UniChip Corp. (GUC)
Type
Silicon IP

Analog

Resolution bits
12 Bit

Files

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about DAC IP core

Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR

In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.

Frequently asked questions about DAC IP cores

What is 40nm LP 2.5V/1.1V 12bit 80Mhz Current Steering DAC [2ch]?

40nm LP 2.5V/1.1V 12bit 80Mhz Current Steering DAC [2ch] is a DAC IP core from Global UniChip Corp. (GUC) listed on Semi IP Hub. It is listed with support for tsmc Silicon Proven.

How should engineers evaluate this DAC?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DAC IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP