Vendor: NTLab Category: High-Speed

4 Gbps DDR CML receiver and transmitter

055TSMC_CML_01 is a library including: - CML receiver (CML_RX); - CML transmitter (CML_TX).

TSMC 55nm GP Pre-Silicon View all specifications

Overview

055TSMC_CML_01 is a library including:
- CML receiver (CML_RX);
- CML transmitter (CML_TX).
The CML_RX block is intended to receive a CML signal and convert it to a CMOS signal. The CML_TX block is intended to convert signal from CMOS to CML standard and transmit CML signal to external circuits. CML_TX has pre-emphasis circuit.
IP technology: TSMC 55nm CMOS EF technology.
IP status: pre-silicon verification.
Total area:
- CML_RX – 121×121 um2;
- CML_TX – 110×171 um2.

Key features

  • TSMC CMOS 55 nm
  • TIA/EIA-644 LVDS standards
  • Data rate (receive/transmit): up to 4 Gbps (DDR mode)
  • 1.2V digital voltage supply
  • 1.2V core voltage supply
  • 1.2V CMOS input/output logic control signals
  • Temperature range: -40 °C to + 85 °C

Block Diagram

Applications

  • Point-to-point data transmission
  • Multidrop buses
  • Clock distribution
  • Backplane receiver
  • Backplane data transmission
  • Cable data transmission

What’s Included?

  • Schematic or NetList
  • Abstract model (.lef and .lib files)
  • Layout view (optional)
  • Behavioral model (Verilog)
  • Extracted view (optional)
  • GDSII
  • DRC, LVS, antenna report
  • Test bench with saved configurations (optional)
  • Documentation

Silicon Options

Foundry Node Process Maturity
TSMC 55nm GP Pre-Silicon

Specifications

Identity

Part Number
055TSMC_CML_01
Vendor
NTLab
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: Lithuania

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Frequently asked questions about High-Speed I/O Pad IP

What is 4 Gbps DDR CML receiver and transmitter?

4 Gbps DDR CML receiver and transmitter is a High-Speed IP core from NTLab listed on Semi IP Hub. It is listed with support for tsmc Pre-Silicon.

How should engineers evaluate this High-Speed?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this High-Speed IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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