Vendor: Eureka Technology, Inc. Category: Protocol Bridge

32-bit PCI Host Bridge

32-bit PCI Host Bridge

Contact Provider Request Datasheet

Key features

  • Fully supports PCI specification 2.1 and 2.2 protocol.
  • Designed for ASIC and PLD implementations.
  • Fully static design with edge triggered flip-flops.
  • Efficient back-end interface for different types of user devices.
  • Host bridge design includes bus master, bus target and central system functions.
  • Generates standard PCI type 0 and type 1 configuration accesses.
  • Combined bus master and target functions.
    • Master function
      • Initiate PCI memory and IO read/write.
      • Automatic transfer restart on target retry and disconnect
    • Target function
      • Memory or IO read/write
      • Configuration read/write
      • Support for back-end initiated target retry, disconnect and abort.
  • Supports Zero wait state and user inserted wait state burst data transfer.
  • Dual write buffer supports write data posting.
  • User controlled burst and non-burst data transfer.
  • Automatic handling of configuration register read/write access.
  • Supports user initiated target retry, disconnect, abort and delayed transaction.
  • Parity generation and parity error detection.
  • Includes all PCI specific configuration registers.
  • Supports high speed bus request and bus parking.
  • Differentiating Features
    • Backend interface bus type and width selection.
    • Bus arbiter with priority selection.
    • Multiple base address registers.
    • Asynchronous clock domain.
    • Address/Data multiplexing.
    • Backend FIFO interface.
    • Unidirectional host bridge.
    • Burst length and target burst.

Block Diagram

EP430 block diagram

Specifications

Identity

Part Number
EP430
Vendor
Eureka Technology, Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact Eureka Technology, Inc.

Learn more about Protocol Bridge IP core

A comparison of Network-on-Chip and Busses

This whitepaper summarizes the limitations of traditional bus-based approaches, introduces the advantages of the generic concept of NoC, and provides specific data about Arteris’ NoC, the first commercial implementation of such architectures

IP Core for an H.264 Decoder SoC

This paper presents the development of an IP core for an H.264 decoder. This state-of-the-art video compression standard contributes to reduce the huge demand for bandwidth and storage of multimedia applications. The IP is CoreConnect compliant and implements the modules with high performance constraints.

Frequently asked questions about Protocol Bridge IP cores

What is 32-bit PCI Host Bridge?

32-bit PCI Host Bridge is a Protocol Bridge IP core from Eureka Technology, Inc. listed on Semi IP Hub.

How should engineers evaluate this Protocol Bridge?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Protocol Bridge IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP