Vendor: NTLab Category: EEPROM

3.6Kbit EEPROM IP with configuration 28p8w16bit

130GF_EEPROM_08 IP is a nonvolatile electrically erasable programmable read-only memory (EEPROM) with volume 3.6 Kbits, which is …

GlobalFoundries 130nm BCD Pre-Silicon View all specifications

Overview

130GF_EEPROM_08 IP is a nonvolatile electrically erasable programmable read-only memory (EEPROM) with volume 3.6 Kbits, which is organized as 28 pages of 8 words by 16 bit with single-bit output data and parallel write data. Data programming in EEPROM consists of 2 consecutive phases - erasing and writing. Data to be programmed in EEPROM are applied to D1<15:0>, D0<15:0>inputs. The erasing phase is performed by setting BUSY signal to “1” while the ERASE signal is also at “1”. The writing phase is performed by setting BUSY signal to “1” while the WRITE signal is also at “1”. Data D1<15:0>, D0<15:0>, page address ADR_P<4:0> and word address in page ADR_W<2:0> must not be changed throughout the whole cycle of writing (i.e. while HV_ON = “1”). Data reading is performed using the SAMPLE signal.

Memory is optimized for usage in the industrial and commercial applications, requiring low power consumption and supply voltage.

Total area: 0.12 mm2.

ELECTRICAL CHARACTERISTICS

Parameter

Symbol

Conditions

Value

 

Units

min

typ.

max

Supply voltage

VDD

Write mode

 

 

 

 

Read mode

 

 

 

 

Operating temperature range

Tj

-

-40

+27

+125

°C

Clock frequency for internal voltage doubler

FCLK_VDD2

 

-

 

-

 

0.5

 

-

 

MHz

Clock frequency for high voltage pump generator

FCLK_HV

 

-

 

-

 

1

 

-

 

MHz

Reference current

IREF

receiving device: pMOSFET

-

50

-

nA

Access time

tACC

1.2V ≤ VDD ≤ 1.65V

-

0.3

0.4

 

 

us

0.9V ≤ VDD < 1.2V

-

0.3

0.5

0.8V ≤ VDD < 0.9V

-

0.3

0.6

VDD = 0.7V

-

0.3

-

VDD = 0.6V

-

0.7

-

Active pulse width of BUSY signal

TPRG

-

1

2

4

ms

Current consumption in read mode*

IREAD

FSAMPLE = 0.5 MHz

DCSAMPLE = 75%

-

-

0.90

2.60

 

 

 

uA

VDD = 1.0 V

-

0.75

1.70

VDD = 0.9 V

-

0.70

1.60

VDD = 0.8 V

-

0.55

1.40

VDD = 0.7 V

-

0.50

-

VDD = 0.6 V

-

0.45

-

Average current consumption in program mode

IPROG_AVG

 

-

 

-

 

9

 

23

 

uA

Peak current consumption in program mode

IPROG_PEAK

 

-

 

-

 

27

 

41

 

uA

High Level Input Voltage

VIH

For digital inputs

0.85VDD

-

VDD

V

Low Level Input Voltage

VIL

-

-

0.15

V

Block Diagram

Silicon Options

Foundry Node Process Maturity
GlobalFoundries 130nm BCD Pre-Silicon

Specifications

Identity

Part Number
130GF_EEPROM_08
Vendor
NTLab
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: Lithuania

Learn more about EEPROM IP core

Unleashing EEPROM Potential by Going Embedded: Introducing eMemory's NeoEE

EEPROM memory, which recently celebrated its 50th birthday, continues to defy obsolescence. Despite its age, EEPROM remains a mature, reliable, and affordable technology for many electronic systems. As IC designers embed EEPROM onto chips, it has become an integral part of chip design, offering essential benefits to applications such as MCU, PMIC, sensors, and RFID tags.

When Memory Shortages Change Architecture Decisions

For decades, the choice between embedded and external Non-Volatile Memory (NVM) in semiconductor designs has been straightforward. External memory, such as EEPROM, NOR Flash, or NAND Flash, offered lower cost per bit and greater flexibility, making a two-die architecture the default choice across a wide range of applications. That assumption is now being challenged.

Understanding Physical Unclonable Function (PUF)

A growing number of ASICs, microcontrollers and SoCs embed hardware cryptographic accelerators or software cryptographic libraries. The emergence of the Internet of Things (IoT) will call for an even faster adoption. We now can talk about cryptography pervasion.

Types of Storages for Computing System-On-Chips

We are living in an age where we generate the same amount of data each year that has been generated since antiquity. Ever wondered how and where these peta /exa/zetta bytes of data are stored?

CSoC Platform / Digital Subsystem IP for IoT

This paper describes a CSoC platform and configurable digital subsystem IP which can be deployed for development of IOT edge devices. The paper encompasses the different attributes of IOT edge device that can cater multiple industry segments, key features and benefits of CSoC platform, components of the digital subsystem IP that enables rapid prototyping of SoCs for IOT applications.

Frequently asked questions about EEPROM IP cores

What is 3.6Kbit EEPROM IP with configuration 28p8w16bit?

3.6Kbit EEPROM IP with configuration 28p8w16bit is a EEPROM IP core from NTLab listed on Semi IP Hub. It is listed with support for globalfoundries Pre-Silicon.

How should engineers evaluate this EEPROM?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this EEPROM IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP