Vendor: Rambus, Inc. Category: MACsec

1G to 50G Single-Port MACsec Engine with xMII interface and TSN support

The MACsec-IP-361 is a plug-and-play solution for adding MACsec on the xMII side of an Ethernet subsystem.

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Overview

The MACsec-IP-361 is a plug-and-play solution for adding MACsec on the xMII side of an Ethernet subsystem. It is ISO 26262 ASIL-B Ready certified and ideally positioned for designs where the MAC function is tightly integrated with the system-side, for example DMA-MAC Ethernet controllers or switch core IP with integrated MAC modules.

With the MACsec-IP-361, silicon vendors can add line-rate MACsec function using the industry-standard interfaces and achieve seamless operation with an existing Ethernet controller subsystem.

How the MACsec-IP-361 Works

The MACsec-IP-361 engine provides complete MACsec processing for a port. A port may process a single stream or an interleaved stream of IEEE802.3br fragments (if preemption support is included). It contains a flexible classifier with a table of programmable rules with the programmable actions. The transformation engine supports all features and ciphers of the standard MACsec and VLAN-in-clear extension. The processing results are reflected in the MACsec compliant statistics as additional non-standard counters.

The MACsec-IP-361 engine operates as a fixed delay component at the xMII side, preserving accuracy of PTP timestamping and TSN scheduling created by the TSN MAC subsystem. Its operation is transparent for non-packet related information that is sent over the xMII bus.

The target integration would be instantiating the MACsec-IP-361 between an Ethernet MAC and a PCS. The PCS function may reside in a different device, for example, in the PHY. For egress direction, the MAC must be programmed to reserve space for MACsec expansion for example by stretching the IPG or managing the packet rate accordingly.

Key features

  • Packet Interface
    • 10M/100M: MII
    • 1G/2.5G: GMII
    • Optional 10G/25G: XGMII
    • Optional support for IEEE802.3br
    • Separate Rx and Tx clocks
    • Fixed low-latency operation
  • SA and Classification Scaling
    • SA (16 to 512)
    • TCAM rules (16 to 512)
  • Control Interface
    • APB (asynchronous, 32-bit)
  • Interrupts
  • Default Protocol Support
    • Full IEEE 802.1AE-2018 compliance
    • IEEE 802.1AE
    • IEEE 802.1AEbn
    • IEEE 802.1AEbw
    • IEEE 802.1AEcg
    • MACsec with up to 4x VLAN-in-clear
  • Automotive Functional Safety
    • Certified ISO 26262 ASIL-B Ready
  • NIST CAVP compliance for FIPS 140-3 validation
    • Support for basic AES and AES-GCM transformations

Block Diagram

MACsec-IP-361 block diagram

Specifications

Identity

Part Number
MACsec-IP-361
Vendor
Rambus, Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Rambus, Inc.
HQ: USA
Contact Rambus, Inc.

Learn more about MACsec IP core

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Frequently asked questions about MACsec IP cores

What is 1G to 50G Single-Port MACsec Engine with xMII interface and TSN support?

1G to 50G Single-Port MACsec Engine with xMII interface and TSN support is a MACsec IP core from Rambus, Inc. listed on Semi IP Hub.

How should engineers evaluate this MACsec?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this MACsec IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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