12bit 2MSps SAR ADC on TSMC CLN28HPM/HPC
This IP is Successive Approximation Register (SAR) Analog to Digital Converter on CLN28HPM/HPC
Overview
This IP is Successive Approximation Register (SAR) Analog to Digital Converter on CLN28HPM/HPC
Key features
- Conversion method : Successive approximation
- Resolution : 12bit
- Conversion time : 0.5µs
- Differential nonlinearity : -1LSB(Min.)/+2LSB(Max.)
- Integral nonlinearity : -4LSB(Min.)/+4LSB(Max.)
- Supply voltage: VCCA=1.8+/-0.15V
- Analog Input range : 0 to VCCA, single-ended.
- 14ch analog inputs multiplexer included.
Block Diagram
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 28nm | HPC | Available on request |
| TSMC | 28nm | HPM | Available on request |
Specifications
Identity
Analog
Files
Note: some files may require an NDA depending on provider policy.
Provider
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Frequently asked questions about ADC IP cores
What is 12bit 2MSps SAR ADC on TSMC CLN28HPM/HPC?
12bit 2MSps SAR ADC on TSMC CLN28HPM/HPC is a ADC IP core from Renesas listed on Semi IP Hub. It is listed with support for tsmc Available on request.
How should engineers evaluate this ADC?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this ADC IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.