12-bit, 2.5Msps, 3V, 0.4µs, successive approximation register (SAR) analog-to-digital converter (A/D) that is fabricated using TSMC's CLN40LP
The AT40LADC000112206BSAA1 is a 12-bit, 2.5Msps, 3V, 0.4µs, successive approximation register (SAR) analog-to-digital converter (A/D) that is fabricated using TSMC's CLN40LP (CMOS Logic Node 40nm Low Power (LP)) process technology.
Electrical characteristics
| Item | Unit | Spec MIN | Spec TYP | Spec MAX | Description |
|---|---|---|---|---|---|
| Analog operating voltage (VCCA) | V | 2.7 | 3.3 | 3.6 | |
| Digital operating voltage (VDD) | V | 1.04 | 1.2 | 1.26 | |
| Reference voltage (VREF) | V | 2.7 | 3.3 | 3.6 | VCCA ≥ VREF |
| Junction temperature (Tj) | °C | -40 | 25 | 125 | |
| Resolution | bits | 8 | 10 | 12 | selectable |
| Clock frequency (ADCLK) | MHz | - | 60 | 61.5 | |
| Analog input range (Vin) | V | 0 | VREF | Single ended | |
| Analog input channel number | n | - | - | 1 | No multiplexer included |
| Conversion rate (Fconv) | Msps | - | - | 2.5 | ADCLK=60MHz, 12bit |
| Conversion time (Tconv) | µs | 0.4 | - | - | ADCLK=60MHz, 12bit |
| Integral Non-Linearity (INL) | LSB | -2 | - | +2 | 12bit |
| Differential Non-Linearity (DNL) | LSB | -1 | - | +1 | 12bit |
| Absolute accuracy (Abs) | LSB | -4 | - | +4 | 12bit |
| Power consumption (Icc) | mA | - | 0.7 | 1.1 | ADCLK=60MHz, VCCA pin |
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 40nm | LP eFlash | Available on request |
Note: some files may require an NDA depending on provider policy.
12-bit, 2.5Msps, 3V, 0.4µs, SAR Analog-to-Digital Converter IP is a ADC IP core from Renesas listed on Semi IP Hub. It is listed with support for tsmc Available on request.
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