Learn more about Register File IP core
This paper proposes AIA, an Approximate Inference Accelerator designed to empower decision-making and reasoning at the edge.
The authors present four interface-compatible digital IP blocks implemented as standard-cell CMOS on the SkyWater 130 nm process: a process, voltage and temperature (PVT) sensor built from five selectable ring oscillators that also provides a jitter-based true-random-number generator and a frequency-bounds health monitor; a stochastic leaky integrate-and-fire (LIF) neuron with a configurable LFSR, a programmable activation table, and a refractory period; an on-chip spike-timing-dependent plasticity (STDP) controller with a programmable curve and reward-modulated, eligibility-trace, and anti-Hebbian modes; and a memristive-crossbar controller supporting forming, set, reset, read, and automated current-voltage sweep with current-compliance limiting and half-select biasing.
In this article we describe Antmicro’s implementation of a DCLS functionality in the VeeR EL2, a 32-bit core variant from the VeeR family of RISC-V cores hosted by CHIPS Alliance, a fund of the Linux Foundation. We will show how the DCLS module detects errors, explain how to configure DCLS in the VeeR EL2 core, and briefly describe its verification process.
We utilize QuantX, our in-house hardware-aware quantization platform, to generate a CPU-friendly codebook-based quantization technique, Q4X, and demonstrate its effectiveness by integrating it into a private fork of the popular Llama.cpp framework.
Memory safety is a critical concern for modern embedded systems, particularly in security-sensitive applications. This post explores the area impact of adding memory safety extensions to the Ibex RISC-V core, focusing on Physical Memory Protection (PMP) and Capability Hardware Enhanced RISC Instructions for embedded devices (CHERIoT). We synthesise the extended Ibex® cores using a commercial tool targeting the open FreePDK45 process and provide a detailed area breakdown and discussion of the results.
This paper reverse engineers modern NVIDIA GPU cores, unveiling many key aspects of its design and explaining how GPUs leverage hardware-compiler techniques where the compiler guides hardware during execution. In particular, it reveals how the issue logic works including the policy of the issue scheduler, the structure of the register file and its associated cache, and multiple features of the memory pipeline.
