The wait is over - JEDEC Announces JESD79-5, DDR5 SDRAM VIP for High Performance Computing
July 21, 2020
JEDEC recently announced the ratification of JESD79-5 DDR5 SDRAM to support the standardization of next-generation memory devices, catering to demand from rapid expansion in high performance computing and data center applications. This new standard promises to deliver 2X memory bandwidth, 4X larger density dies, and much improved power efficiency (1.1V Vdd). The DDR5 DIMM will operate in dual-channel mode all on its own, with two 40-bit fully independent sub-channels on the same module.
To read the full article, click here
Related Semiconductor IP
- DDR5 MRDIMM PHY and Controller
- DDR5 & DDR4 COMBO IO for memory controller PHY, 4800Mbps on TSMC 12nm
- DDR5 LRRDIMM Verification IP
- DDR5 RDIMM Verification IP
- MRDIMM DDR5 & DDR5/4 PHY & Controller
Related Blogs
- JEDEC UFS 3.0 Now Available in Cadence VIP Portfolio - For Mobile and Automotive Markets
- High Speed Memory in Smart Phones: MIPI UniPro v1.8 for JEDEC UFS v3.0
- DDR5 - Off and Running
- How DFI 5.0 Ensures Higher Performance in DDR5/LPDDR5 Systems?
Latest Blogs
- Rivos Collaborates to Complete Secure Provisioning of Integrated OpenTitan Root of Trust During SoC Production
- From GPUs to Memory Pools: Why AI Needs Compute Express Link (CXL)
- Verification of UALink (UAL) and Ultra Ethernet (UEC) Protocols for Scalable HPC/AI Networks using Synopsys VIP
- Enhancing PCIe6.0 Performance: Flit Sequence Numbers and Selective NAK Explained
- Smarter ASICs and SoCs: Unlocking Real-World Connectivity with eFPGA and Data Converters