DDR4 IP Listing

With sophisticated architecture and technology, the Vendor provides DDR4 IP solution with high performance and low power.

• DDR

DDR4 DFI Verification IP provides an smart way to verify the DDR4 DFI component of a SOC or a ASIC.

• DDR

DDR4 RCD Memory Model provides an smart way to verify the DDR4 RCD component of a SOC or a ASIC.

• DDR

DDR4 DB Memory Model provides an smart way to verify the DDR4 DB component of a SOC or a ASIC.

• DDR

DDR4 DIMM Memory Model provides an smart way to verify the DDR4 DIMM component of a SOC or a ASIC.

• DDR

DDR4 3DS DIMM Memory Model provides an smart way to verify the DDR4 3DS DIMM component of a SOC or a ASIC.

• DDR

DDR4 3DS Memory Model provides an smart way to verify the DDR4 3DS component of a SOC or a ASIC.

• DDR

DDR4 Memory Model provides an smart way to verify the DDR4 component of a SOC or a ASIC.

• DDR

DDR4 DFI Synthesizable Transactor provides a smart way to verify the DDR4 DFI component of a SOC or a ASIC in Emulator or FPGA pl…

• DDR

DDR4 3DS Synthesizable Transactor provides an smart way to verify the DDR4 3DS component of a SOC or a ASIC in Emulator or FPGA p…

• DDR

DDR4 Synthesizable Transactor provides a smart way to verify the DDR4 component of a SOC or a ASIC in Emulator or FPGA platform.

• DDR

DDR4 is full-featured, easy-to-use, synthesizable design, compatible with DDR4 JESD79-4, JESD79-4A, JESD79-4A_r2, JESD79-4B, JESD…

• DDR

DDR4 is full-featured, easy-to-use, synthesizable design, compatible with DDR4 JESD79-4, JESD79-4A, JESD79-4A_r2, JESD79-4B, JESD…

• DDR
• In Production
• Immediately

The DDR4 IO is used to transfer the Command/Address/Clk and Data between the memory controller PHY and the DRAM device.

• SMIC
• 40nm
• Silicon Proven

The DDR5&DDR4 COMBO IO is used to transfer the Command/Address/Clk and Data between the memory controller PHY and the DRAM device.

• TSMC
• 12nm
• FFC

The DDR4 Memory Controller Verification IP ensures compliance with DDR4 standards, validating high-speed data transfer, read/writ…

• DDR

First to market with full DDR4 LRDIMM support.This Cadence® Verification IP (VIP) supports the JEDEC® DDR4 Unbuffered DIMM (UDIMM…

• DDR

DDR4 DFI Assertion IP provides an efficient and smart way to verify the DFI DDR4 designs quickly without a testbench.

• DDR

DDR4 Assertion IP provides an efficient and smart way to verify the DDR4 designs quickly without a testbench.

• DDR

The Synopsys DDR4 multiPHY is a physical (PHY) layer IP interface solution for PC/consumer and mobile ASICs, ASSPs, system-on- ch…

• UMC
• 28nm
• HPC
• Available on request