Neural Network IP Listing

The Dynamic Neural Accelerator II (DNA-II) is a -efficient and neural network IP core that can be paired with any host processor.

• NPU

The Series3NX-F brings programmable extensibility to the Series3NX architecture.

• NPU

The Neural-Network Accelerators (NACC) improves the inference performance of neural networks.

• NPU

The new Synopsys ARC® NPX Neural Processing Unit (NPU) IP family delivers the industry’s highest performance and support for the …

• NPU
• Available on request
• Available

The Cadence® Tensilica® NNE 110 offers an energy-efficient hardware-based AI engine that can be paired with a Tensilica based DSP.

• Edge AI Accelerator

Kneron NPU IP Series are neural network processors that have been designed for edge devices.

• Edge AI Accelerator

The Xilinx® Deep Learning Processor Unit (DPU) is a programmable engine dedicated for convolutional neural network.

• NPU

Take advantage of the power of FPGA’s parallel processing to implement CNNs.

• NPU

Our IP Core enables you to create chips for automotive nn acceleration with excellent sustained performance and low power under r…

• Edge AI Accelerator

With more than double the performance of the previous generation, the PowerVR AX3595 is the flagship of our new range of single-c…

• NPU

With 4.0 TOPS in a smaller silicon area than its predecessor, the PowerVR AX3385 is suitable for high-end smartphones, smart came…

• NPU

The PowerVR AX3365 delivers up to 2.0 TOPS performance in a small silicon area.

• NPU

The PowerVR AX3145 is an ideal choice for more cost-sensitive devices with basic performance requirements.

• NPU

PowerVR AX3125 is a cost-sensitive solution for low-power applications – i.e.

• NPU

The inference neural processing unit (NPU) IP is suitable for high-performance edge devices including automotive, cameras, and mo…

• NPU
• Now

Scalable and Power-Efficient Neural Processing Units The Neo NPUs offer energy-efficient hardware-based AI engines that can be pa…

• Edge AI Accelerator

Features a optimized network model compiler that reduces DRAM traffic from intermediate activation data by grouped layer partitio…

• NPU
• Production-and market-proven
• Now

Hierarchical scalability is the foundation principle of the Fibonacci machine-learning (ML) system-on-chip (SoC).

• Edge AI Accelerator

The VIP9400 processing family offers programmable, scalable and extendable solutions for markets that demand real time and AI dev…

• NPU
• Silicon Integration
• Now

Ceva-NeuPro-M is a scalable NPU architecture, ideal for transformers, Vision Transformers (ViT), and generative AI applications, …

• NPU
• Available