Shrinking LLMs with Self-Compression
Discover how Self-Compression effectively reduces language model sizes, enhancing efficiency for on-device inference while maintaining predictive quality, ideal for resource-limited settings.
Vendor:
Imagination Technologies Group Ltd.
Category:
NPU
PowerVR Neural Network Accelerator - cost-sensitive solution for low power and smallest area
PowerVR AX3125 is a cost-sensitive solution for low-power applications – i.e.
Overview
PowerVR AX3125 is a cost-sensitive solution for low-power applications – i.e. where power draw is a key issue. It can run at up to 0.6 TOPS in IoT devices, entry-level smart cameras, embedded systems or entry-level smartphones. The minimal silicon area and low-power requirements make it an ideal partner for LP-WAN or solutions with battery power constraints or where energy harvesting is in operation.
Key features
- API support
- IMG DNN API
- Android NN HAL
- Framework Support
- Caffe
- TensorFlow
- Bus interface
- AXI4
- Memory system
- Virtual Memory
- TOPS
- 0.6 TOPS
- MACs per clock rate
- 8-bit: 256 MACs/clk
- 16-bit: 64 MACs/clk
- Architecture
- PowerVR Series3NX
- Markets
- IoT devices
- Entry-level smart cameras
- Embedded systems
- Features
- Security
- Lossless weight compression
Specifications
Identity
Part Number
PowerVR AX3125
Vendor
Imagination Technologies Group Ltd.
Type
Silicon IP
Files
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Provider
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Frequently asked questions about NPU IP cores
What is PowerVR Neural Network Accelerator - cost-sensitive solution for low power and smallest area?
PowerVR Neural Network Accelerator - cost-sensitive solution for low power and smallest area is a NPU IP core from Imagination Technologies Group Ltd. listed on Semi IP Hub.
How should engineers evaluate this NPU?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this NPU IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.