32-bit PCI Bus Target
- PCI
- Now
- PCI Specification 2.2 Proto…
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
32-bit PCI Bus Target
32-bit PCI Bus Master/Target
PowerPC to PCI Bridge
PowerPC Bus Slave
PowerPC Bus Master
PowerPC Bus Arbiter
Low-power 12-bit 80 MHz ADC + 640 MHz DAC
The data converter IP portfolio includes low-power SAR ADCs, flash ADCs, and high-speed I/Q DACs optimized for RF and baseband pa…
CCSDS 121/123 Lossless Compression
The GRSHYLOC IP enables lossless compression for multi-spectral and hyper-spectral images according to the CCSDS121 and CCSDS123 …
HOTLink II IP Core
IP
MIPI DSI-2 v2.0 TRANSMITTER FOR COMBO C/DPHY
IP
12-bit, 400 MSPS SAR ADC - TSMC 12nm FFC
The A12B400M is a low-power, high-speed analog to digital converter (ADC) intellectually property (IP) design block.
12-bit, 9.2 GSPS Pipeline ADC - GlobalFoundries 22nm
The A12B9G is a low-power, high-speed analog to digital converter (ADC) intellectual property (IP) design block.
12-bit, 200 MSPS Pipeline ADC - TSMC 28nm
The A12B200M is a low-power, analog to digital converter (ADC) intellectually property (IP) design block.
UCIe-S PHY for Standard Package (x32) in TSMC (N3P)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data c…
UCIe-S PHY for Standard Package (x16) for Automotive in TSMC (N5A)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data c…
PCIe 7.0 PHY in TSMC (N5, N3P)
The multi-channel PHY IP for PCI Express® (PCIe®) 7.0 meets today’s demands for higher bandwidth and power efficiency across back…
LPDDR4 multiPHY V2 in UMC (28nm)
The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-o…
MIPI D-PHY v1.2 TX 4 Lanes in Samsung (8nm)
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and per…
MIPI D-PHY v1.2 RX 2 Lanes in Samsung (8nm)
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and per…