IP
- Multi-Protocol PHY
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
IP
Brite Semiconductor offers customers a variety of ADC IP models, and the main architecture includes SAR and Pipeline, with the sa…
ARINC 664 End System Controller
ARINC 664 End System Controller
10G TCP+UDP Offload+EMAC+PCIe+Host IF Ultra-Low Latency (SXTOE+UOE+PCIe)
INT 25012 is the only SOC IP Core that implements a full 10G bit TCP and UDP Stack in Handcrafted, Ultra-High Performance, , Flex…
10G TCP+UDP Offload+EMAC+Host_IF Ultra-Low Latency (SXTOE+UOE)
INT 25011 is the only SOC IP Core that implements a full 10G bit UDP Stack in Handcrafted, Ultra-High Performance, , Flexible and…
1G TCP Offload Engine TOE+MAC+PCIe+Host_IF Ultra-Low Latency (STOE+PCIe)
INT 2012 is the only SOC IP Core that implements a full 1G bit TCP Stack in Handcrafted, Ultra Low Latency and Very High Performa…
1G TCP Offload Engine TOE+MAC+Host_IF Ultra-Low Latency (STOE)
INT 1011 is the only SOC IP Core that implements a full 1G bit TCP Stack in Handcrafted, Ultra Low Latency and Very High Performa…
1G UDP Offload+MAC+PCIe+Host_IF Ultra-Low Latency (SUOE+PCIe)
INT 1512 is the only SOC IP Core that implements a full 1G bit UDP Stack in Handcrafted, Ultra High Performance, , Flexible and S…
1G_UDP_Offload+MAC+Host_IF Ultra-Low Latency (SUOE)
INT 1511 is the only SOC IP Core that implements a full 1G bit UDP Stack in Handcrafted, Ultra High Performance, , Flexible and S…
Speedcore embedded FPGA (eFPGA) IP has brought the performance and flexibility of programmable logic to ASICs and SoCs.
LDS SATA RECORDER IP ON ARTIX 7
IP
This 3GPP LTE IP (compliant to release 9) eNodeB PHY Baseband and MAC-PHY API.
UFS 3.1 Silicon Proven 2.1 HOST
IP
UFS 3.1 Silicon Proven 2.1 Device, Host
IP
UniPro 2.0 & Silicon Proven v1.8, v1.61
IP
eMMC 4.5 Card Slave Controller
eMMC 4.5 Card Slave Controller
Noesis Technologies ntT1_G704 Framer/Deframer is designed for T1 networks and is compliant with ITU recommendations G.704, G.706,…
Ultra-low-power Processor based on RISC-V Architecture
The icyflex-V processor is a new ultra-low-power core based on the RISC-V 32-bit ISA, a long-awaited addition to the CSEM icyflex…
SD 3.0/eMMC 4.5 Host Controller
SD 3.0/eMMC 4.5 Host Controller
eMMC/MMC Card Slave Controller
eMMC/MMC Card Slave Controller