Vendor: Eureka Technology, Inc. Category: PCI

32-bit PCI Bus Target

32-bit PCI Bus Target

Key features

  • Fully supports PCI specification 2.1 and 2.2 protocol.
  • Designed for ASIC and PLD implementations.
  • Fully static design with edge triggered flip-flops.
  • Efficient back-end interface for different types of user devices.
  • Supports compact PCI, Cardbus, Mini-PCI and Power Management.
  • Supports zero wait state data burst transfer to maximize memory bandwidth.
  • Zero wait state and user inserted wait state burst data transfer.
  • Dual write buffer supports write data posting.
  • User controlled burst and non-burst data transfer.
  • Multiple address mapping to memory and IO address spaces.
  • Automatic handling of configuration register read/write access.
  • Supports back-end initiated target retry, disconnect and abort.
  • Supports delayed data transaction initiated by user logic.
  • Parity generation and parity error detection.
  • Includes all PCI specific configuration registers.

Block Diagram

Specifications

Identity

Part Number
EC125
Vendor
Eureka Technology, Inc.
Type
Silicon IP

Files

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Provider

Learn more about PCI IP core

PCI Express 3.0 needs reliable timing design

PCI Express (PCIe) is an important standard for chip-to-chip communications and serves as a standard for connecting motherboards to peripheral cards. It can be challenging, however, to implement the reference clock so that it meets the various requirements of the PCIe standard.

Frequently asked questions about PCI IP cores

What is 32-bit PCI Bus Target?

32-bit PCI Bus Target is a PCI IP core from Eureka Technology, Inc. listed on Semi IP Hub.

How should engineers evaluate this PCI?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PCI IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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