SkyeChip IP Cores

Bandwidth and area optimized low power memory interface solution tuned for AI, HPC, data centers and networking conforming to HBM…

• TSMC
• 7nm
• N7

The HBM3 IP consists of a PHY and memory controller optimized for Samsung SF4X process to support the HBM3 memory standard (JESD2…

• HBM

High-speed configurable I/O capable of signaling speeds of up to 3.2 GT/s supporting the following I/O standards

• GPIO

Lightweight die-to-die interconnect solution consisting of the Physical Layer, Die-to-Die Layer and Protocol Layer optimized for …

• UCIe

Performance (bandwidth and latency) optimized non-coherent NOC solution that significantly reduces silicon wire utilization, resu…

• Network-On-Chip
• Since April 2024

High performance, low power and area efficient memory interface solutions conforming to LPDDR5/5X (JESD209-5C) JEDEC standard

• LPDDR

Low Power RISCV CPU IP

• CPU

MIPI D-PHY

• MIPI PHY

Bandgap

• Voltage Reference

High-Speed PLL

• PLL

Scalable and area efficient interconnect solution optimized for memory coherent systems

• Network-On-Chip
• Since April 2024

High performance, low power and area efficient memory interface solutions conforming to DDR5 (JESD79-5) and DDR4 (JESD79-4) JEDEC…

• DDR