Vendor: Cadence Design Systems, Inc. Category: Single-Protocol PHY

USB 2.0 PHY

Proven PHY IP for USB Device, Host, and OTG with small footprint and low active power Architected to quickly and easily integrate…

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TSMC 7nm N7+ Silicon Proven View all specifications

Overview

Proven PHY IP for USB Device, Host, and OTG with small footprint and low active power

Architected to quickly and easily integrate into any SoC, the Cadence® USB 2.0 On-The-Go (OTG) PHY IP connects seamlessly to a Cadence or third-party UTMI-compliant controller. The IP provides you with a cost-effective, low-power solution for demanding applications. It offers SoC integrators the advanced capabilities and support that exceed the requirements of high-performance designs and implementations. The Cadence USB 2.0 OTG IP is silicon-proven and has been extensively validated with multiple hardware platforms.

Key features

  • Designed to the USB 2.0 specification, and operates at High Speed (480Mbps), Full Speed (12Mbps), and Low Speed (1.5Mbps)
  • Complies with the UTMI v1.05 specification
  • Multiple reference clock supported from 9.6MHz up to 52MHz
  • 8-bit 60MHz and 16-bit 30MHz parallel interfaces
  • Battery Charging Specification v1.2
  • Supports link power management (LPM)
  • APB and JTAG interface

Block Diagram

USB 2.0 PHY block diagram

Applications

  • Automotive,
  • Communications,
  • Consumer Electronics,
  • Data Processing,
  • Industrial and Medical,
  • Military/Civil Aerospace,
  • Others

What’s Included?

  • Verilog behavioral modules for PHY module
  • Verilog testbench with configuration files and sample tests
  • Liberty timing model
  • Layout abstract in LEF format
  • GDSII with flat netlist for LVS

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Silicon Options

Foundry Node Process Maturity
TSMC 7nm N7+ Silicon Proven

Specifications

Identity

Part Number
USB 2.0 PHY
Vendor
Cadence Design Systems, Inc.

Provider

Cadence Design Systems, Inc.
HQ: USA
If you want to achieve silicon success, let Cadence help you choose the right IP solution and capture its full value in your SoC design. Cadence® IP solutions offer the combined advantages of a high-quality portfolio, an open platform, a modern IP factory approach to quality, and a strong ecosystem. Now you can tackle IP-to-SoC development in a system context, focus your internal effort on differentiation, and leverage multi-function cores to do more, faster. The Cadence IP Portfolio includes silicon-proven Tensilica® IP cores, analog PHY interfaces, standards-based IP cores, verification IP cores, and other solutions as well as customization services for current and emerging industry standards. The Cadence IP Factory provides you with an automated approach to the customization, delivery, and verification of SoC IP. As a result, you can spend more time on differentiation, with the assurance that you'll meet your performance, power, and area requirements. Choosing Cadence IP enables you to design with confidence because you have more freedom to innovate your SoCs with less risk and faster time to market.
Contact Cadence Design Systems, Inc.

Learn more about Single-Protocol PHY IP core

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Can MIPI and MDDI Co-Exist?

Since MIPI and MDDI standards both target interfaces to cameras and displays on mobile devices, are two separate standards really needed?

Frequently asked questions about Single-Protocol PHY IP

What is USB 2.0 PHY?

USB 2.0 PHY is a Single-Protocol PHY IP core from Cadence Design Systems, Inc. listed on Semi IP Hub. It is listed with support for tsmc Silicon Proven.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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