How Secure DDR Interfaces Protect DRAM from Memory Attacks
Brett Murdock, Dana Neustadter (Synopsys)
Vendor:
Key ASIC
Category:
DDR
DDR3 and DDR4 Controller and PHY on TSMC 12nm
This DDR3/4 IP combo solution presented, is meticulously designed for high performance and low power consumption, utilizing sophi…
Overview
This DDR3/4 IP combo solution presented, is meticulously designed for high performance and low power consumption, utilizing sophisticated architecture and advanced technology. Fabricated in TSMC’s 12nm CMOS process, this solution includes both controller and PHY IPs, providing comprehensive support for DDR3 and DDR4 memory interfaces. The DDR4 interface achieves speeds of up to 3200Mbps. Architecturally, it features a Multiport AMBA AXI interface, with configurable port numbers and support for both asynchronous and synchronous AXI ports. The PHY interface integrates a DFI 4.0 compatible design, with three embedded de-skew PLLs to enhance jitter performance.
Key features
- Support DDR4 up to 3200Mbps speed, DDR3 up to 2133Mbps
- Support Multiport AMBA AXI4 interface, port number, asynchronous or synchronous AXI port, data width, FIFO depth, and command queue depth configurable;
- Support DFI4.0 compliant interface between controller and PHY;
- Support 2 ranks, max density up to 8GB;
- Support automatic temperature monitor and refresh rate adjust;
- Support CA, write, read VREF eye training and per-bit de-skew training, write leveling training;
- Support Inline BIST and SIPI/LFSR/USER patterns;
- Support DDRPHY loopback test;
- Support fully pin-mux easy for PKG/PCB routing;
- Support mask write, write/read DBI;
- Support 2T CA timing, CA parity, and gear down mode; (DDR4)
- Support ECC (error correcting code), 32/64bit data+8bit ECC, correct 1bit-error and detect 2bit-error; (DDR4)
Block Diagram
KAT12DDR34 block diagram
Benefits
- Optimized for high bandwidth and low latency
- Suitable for high-performance, low-power SoC integration
- Simplifies DDR integration with pre-verified PHY and controller
- Reduced risk with built-in training, BIST, and loopback features
Applications
- AI SoC, Consumer Electronics, Networking, Industrial Control, Storage Controllers
What’s Included?
- Datasheet with integration guidelines
- Register Map, Timing Sheet
- Encrypted RTL + Netlist + Layout (.LEF, GDS, SDF)
- Verification environment & testbenches
- SDC constraints
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 12nm | FFC | Available on request |
Specifications
Identity
Part Number
KAT12DDR34
Vendor
Key ASIC
Type
Silicon IP
Controller / PHY
Controller
,
PHY
Provider
Key ASIC
HQ:
Malaysia
Key ASIC was incorporated in the year 2005. In 2006, we were awarded Multimedia Super Corridor (MSC) Status by the Malaysia Digital Economy Corporation (MDEC). We started with the design of IP, ASIC, and SoC. In 2009, we were listed on the main board of KLSE. Khazanah and CIMB are our main investors.
Key ASIC is not only a leading ASIC / SoC design service company, we are also a turnkey service company from spec-in to system module that focuses on AI chips, IoT, and medical applications. We are committed to providing customers with competitive SoC professional one-stop design services in terms of PPA (Performance, Power, and Area).
Based in Kuala Lumpur, Malaysia with R&D Centers in Malaysia and Tai Yuen Hi-Tech Industrial Park Taiwan, Key ASIC provides ODM and OEM of ASIC design services from Specification, RTL, Netlist to silicon, as well as process migration from GDSII.
Our experienced SoC designer and engineers combined with extensive manufacturing, logistics resources, and a flexible engagement model can provide Key ASIC customers with a comprehensive support system for modular ASIC innovation from IP development through prototype to production.
Learn more about DDR IP core
The complete series of high-end DDR IP solutions of Innosilicon is industry-leading and across major foundry processes
In recent years, emerging industries such as AI, Internet of Things, 5G, and intelligent networked vehicles have flourished, and the high requirements for performance have greatly increased the scale and complexity of chips, constantly challenging IP limitations.
Secure DDR DRAM Against Rowhammer, RAMBleed, and Cold-Boot Attacks
Dana Neustadter, Senior Product Manager for Security Solutions, and Brett Murdock, Director, Product Line Management for Memory Interface IP, Synopsys Solutions Group
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This whitepaper provides an overview of the JEDEC memory standards to help SoC designers select the right memory solution, including IP, that best fits their application requirements.
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Frequently asked questions about DDR Interface IP
What is DDR3 and DDR4 Controller and PHY on TSMC 12nm?
DDR3 and DDR4 Controller and PHY on TSMC 12nm is a DDR IP core from Key ASIC listed on Semi IP Hub. It is listed with support for tsmc Available on request.
How should engineers evaluate this DDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.