UCIe-S (Gen2) Compatible PHY for Standard Package (x16) in TSMC N3P, North/South Orientation

Synopsys UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale data center, AI, and networking applications. The PHY’s flexible architecture supports standard and advanced package technologies and allows up to 21Tbps/mm of data to travel at data rates up to 64Gbps. The IP offers maximum performance with low BER, minimum latency, and implementation flexibility. Synopsys UCIe PHY IP delivers high energy efficiency with an optimized architecture using a single reference clock feature, low-voltage signaling, and hardware-based initialization. The comprehensive testability feature with mission mode singal integrity monitors ensures die, die-to-die, and multi-die design health from in-design to in-field. Robust die-to-die link operation is ensured with embedded training and calibration algorithms. The PHY is compliant with the latest release of the UCIe specification, ensuring successful interoperability between heterogeneous dies.

• Supports data rates up to 64Gb/s and bandwidth density of 21Tbps/mm
• Compliant with the latest UCIe specification
• Supports high-density advanced packaging technologies such as silicon interposer, silicon bridge, and RDL fanout
• Supports standard packaging technologies such as organic substrate and laminate
• Hardware-based initialization & sideband vendor message support
• 100 MHz single reference clock architecture
• Supports on-chip interconnect fabrics including AXI, CHI C2C, CXS, PCIe, CXL, and streaming