UART Verification IP
UART Verification IP provides an smart way to verify the UART component of a SOC or a ASIC.
Overview
UART Verification IP provides an smart way to verify the UART component of a SOC or a ASIC. The SmartDV's UART Verification IP is fully compliant with standard UART 16550 Specification and provides the following features.
UART Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
UART Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
Key features
- Fully compatible with 16550.
- Transmit and receive commands allow the user to transmit and receive UART data.
- Support additional functionality of IRDA, RS232, RS422, RS485 and GPIO.
- Configurable baud rate.
- Full duplex operation.
- Fully configurable serial interface.
- Supports character width from 1 bit to 32 bits.
- Supports number of stop bit configuration.
- Supports different types of parity insertion
- Even parity
- Odd parity
- Space parity
- Mark parity
- No parity
- Error injection capability
- Parity error
- Framing error
- Configurable receive FIFO depth.
- Supports constraints Randomization.
- Callbacks in transmitter, receiver and monitor for user processing of data.
- On-the-fly protocol and data checking.
- Auto CTS/auto RTS hardware flow control.
- GPIO are supported using read and write commands.
- Supports IRDA protocol.
- Ability to transmit strings to help verification of SOC.
- Notifies the testbench of significant events such as transactions, warnings, and protocol violations.
- UART Verification IP comes with complete testsuite to verify each and every feature of UART specification.
- Status counters for various events in bus.
- Functional coverage for complete 16550 features.
- Supports 16 General purpose output and input pins.
- Monitor detects following
- Parity errors
- Framing error
Block Diagram
Benefits
- Faster testbench development and more complete verification of UART designs.
- Easy to use command interface simplifies testbench control and configuration of TX and RX.
- Simplifies results analysis.
- Runs in every major simulation environment.
What’s Included?
- Complete regression suite containing all the UART testcases.
- Examples showing how to connect various components, and usage of BFM and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation contains User's Guide and Release notes.
Files
Note: some files may require an NDA depending on provider policy.
Specifications
Identity
Provider
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Frequently asked questions about UART IP cores
What is UART Verification IP?
UART Verification IP is a UART IP core from SmartDV Technologies listed on Semi IP Hub.
How should engineers evaluate this UART?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this UART IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.