Vendor: SmartDV Technologies Category: UART

UART Verification IP

UART Verification IP provides an smart way to verify the UART component of a SOC or a ASIC.

Overview

UART Verification IP provides an smart way to verify the UART component of a SOC or a ASIC. The SmartDV's UART Verification IP is fully compliant with standard UART 16550 Specification and provides the following features.

UART Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

UART Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key features

  • Fully compatible with 16550.
  • Transmit and receive commands allow the user to transmit and receive UART data.
  • Support additional functionality of IRDA, RS232, RS422, RS485 and GPIO.
  • Configurable baud rate.
  • Full duplex operation.
  • Fully configurable serial interface.
  • Supports character width from 1 bit to 32 bits.
  • Supports number of stop bit configuration.
  • Supports different types of parity insertion
    • Even parity
    • Odd parity
    • Space parity
    • Mark parity
    • No parity
  • Error injection capability
    • Parity error
    • Framing error
  • Configurable receive FIFO depth.
  • Supports constraints Randomization.
  • Callbacks in transmitter, receiver and monitor for user processing of data.
  • On-the-fly protocol and data checking.
  • Auto CTS/auto RTS hardware flow control.
  • GPIO are supported using read and write commands.
  • Supports IRDA protocol.
  • Ability to transmit strings to help verification of SOC.
  • Notifies the testbench of significant events such as transactions, warnings, and protocol violations.
  • UART Verification IP comes with complete testsuite to verify each and every feature of UART specification.
  • Status counters for various events in bus.
  • Functional coverage for complete 16550 features.
  • Supports 16 General purpose output and input pins.
  • Monitor detects following
    • Parity errors
    • Framing error

Block Diagram

Benefits

  • Faster testbench development and more complete verification of UART designs.
  • Easy to use command interface simplifies testbench control and configuration of TX and RX.
  • Simplifies results analysis.
  • Runs in every major simulation environment.

What’s Included?

  • Complete regression suite containing all the UART testcases.
  • Examples showing how to connect various components, and usage of BFM and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation contains User's Guide and Release notes.

Files

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
UART VIP
Vendor
SmartDV Technologies

Provider

SmartDV Technologies
HQ: India
At SmartDV Technologies™, we believe there’s a better way to approach semiconductor intellectual property (IP) for integrated circuits. We’ve been focused exclusively on IP since 2007—so whether you’re sourcing standards-based design IP for your next SoC, ASIC, or FPGA, or seeking verification solutions (VIP) to put your chip design through its paces, you’ll find SmartDV’s IP straightforward to integrate. By combining proprietary SmartCompiler™ technology with the knowledge of hundreds of expert engineers, SmartDV can customize IP to meet your unique design objectives: quickly, economically, and reliably. Don’t allow other suppliers to force onesize-fits-all cores into your chip design. Get the IP you need, tailored to your specifications, with SmartDV: IP Your Way.

Learn more about UART IP core

Capturing a UART Design in MyHDL & Testing It in an FPGA

The universal asynchronous receiver/transmitter (UART) is an old friend to embedded systems engineers. It's probably the first communications protocol that we learn in college. In this article, we will design our very own UART using MyHDL.

Integrating Post-Quantum Cryptography (PQC) on Arty-Z7

Post-quantum cryptography (PQC) is moving from theory to engineering reality. With NIST-standardized algorithms ML-KEM (FIPS 203) and ML-DSA (FIPS 204) now finalized, FPGA developers face a practical challenge: How to integrate these algorithms efficiently on resource-constrained hardware?

How to design secure SoCs, Part V: Data Protection and Encryption

In today’s connected world, where data is a crucial asset in SoCs, Part V of our series explores how to protect and encrypt data, whether at rest, in transit, or in use building on our earlier blog posts of the series: Essential security features for digital designers, key management, secure boot, and runtime integrity.

Not all overvoltage tolerant GPIOs are the same

Most foundries provide GPIO libraries to their fabless customers. These libraries contain different elements like supply/ground pads, analog I/Os, digital I/Os, corner cells, filler cells, power-on-reset circuits. Frequently the foundry includes cells for different voltage domains. In 40nm CMOS the IC designer can use cells for 1.8V, 2.5V and 3.3V for instance.

Frequently asked questions about UART IP cores

What is UART Verification IP?

UART Verification IP is a UART IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this UART?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this UART IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP