Vendor: Synopsys, Inc. Category: GPIO

TSMC N6 1.8V/3.3V Fail-Safe Fail-Tolerant SMBus

Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliabilit…

Contact Provider Request Datasheet
TSMC 6nm N6 View all specifications

Overview

Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their SoCs targeting mobile, automotive, and high-performance computing (HPC) applications. The IP is silicon-proven and available in several foundries and process technologies from 3nm to 22nm.

Synopsys GPIO library is designed to support multiple voltages; it offers a complete set of support cells (supply, corner spacers, diode breakers, terminators) required to create complete I/O pad rings for system-on-chips (SoCs). The library is compatible with flip-chip packaging. The GPIO driver pad incorporates the Schmitt-Trigger function, programmable drive strength, and pull-up/down resistors, with robust HBM and CDM ESD protection. Synopsys’ broad GPIO IP offering helps achieve your SoC design’s critical power, performance, and area (PPA) requirements, delivering low-risk solutions in a fast time-to-market.

Synopsys GPIO IP includes High-Speed Test IO, delivering a breakthrough solution that empowers test engineers and chiplet designers to conduct high-speed, efficient testing of advanced semiconductor designs, while also reducing hardware complexity and costs.

Key features

  • Supports 1.8V/2.5V/3.3V mixed-voltage-tolerant/failsafe output buffer
  • Fully programmable output driver strengths, input Schmitt trigger, and output slew rate
  • Supports circuit-under-pad (CUP), non-CUP-inline and staggered-bond pad placement
  • Supports retention and bus-keeper feature
  • Operating speed in excess of 250MHz
  • Robust ESD (up to 7A CDM, 2KV HBM) and latch-up protection circuitry
  • Automotive G1/G2 supported, ASIL-B certified
  • Silicon-validated IP
  • Available in multiple foundries and a wide range of technology nodes

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Silicon Options

Foundry Node Process Maturity
TSMC 6nm N6 —

Specifications

Identity

Part Number
dwc_io_ts6ff_af_3p3v1p8v_smbus_fsft
Vendor
Synopsys, Inc.

Provider

Synopsys, Inc.
HQ: USA
Synopsys is a leading provider of high-quality, silicon-proven semiconductor IP solutions for SoC designs. The broad Synopsys IP portfolio includes logic libraries, embedded memories, analog IP, wired and wireless interface IP, security IP, embedded processors and subsystems. To accelerate IP integration, software development, and silicon bring-up, Synopsys’ IP Accelerated initiative provides architecture design expertise, pre-verified and customizable IP subsystems, hardening, and signal/power integrity analysis. Synopsys' extensive investment in IP quality, comprehensive technical support and robust IP development methodology enables designers to reduce integration risk and accelerate time-to-market.
Contact Synopsys, Inc.

Learn more about GPIO IP core

GPIO Solutions for CERN’s Radiation-Hardened Applications

For over a decade, Sofics has collaborated with CERN, the European Organization for Nuclear Research. Sofics has delivered advanced GPIO cells tailored for radiation-hardened applications, supporting CERN’s groundbreaking particle physics experiments.

A Generic Solution to GPIO verification

This paper provides a complete solution to the GPIO Verification for any SoC. GPIO interface is available in every ASIC. To avoid duplicate efforts and (save) time to verify the GPIO interface, we have produced this Generic GPIO verification suite. It is a UVM-based verification environment, with all the necessary subcomponents that are required to verify any GPIO design.

Integrating Post-Quantum Cryptography (PQC) on Arty-Z7

Post-quantum cryptography (PQC) is moving from theory to engineering reality. With NIST-standardized algorithms ML-KEM (FIPS 203) and ML-DSA (FIPS 204) now finalized, FPGA developers face a practical challenge: How to integrate these algorithms efficiently on resource-constrained hardware?

From I2C to I3C: Evolution of Two-Wire Communication in Embedded Systems

The I2C (Inter-Integrated Circuit) Bus invented in 1980 by Philips Semiconductors (NXP Semiconductors today) was a massive step forward in simplifying communications in embedded systems. It is a simple two-wire interface for synchronous, multi-master/multi-slave, single ended serial communication. Fast forward 45 years to today and it is still widely used for attaching low speed peripheral Integrated Circuits (ICs), processors and microcontrollers. But silicon today has changed...

One Platform, Five Libraries: Certus Semiconductor’s I/O IP Portfolio for Every Application on TSMC 22nm ULL/ULP Technologies

Certus Semiconductor’s I/O libraries for TSMC’s 22nm ultra-low leakage (22ULL) and 22nm ultra-low power (22ULP) technologies offer robust, high-performance solutions tailored to a wide range of SoC designs — from ultra-low power IoT nodes to demanding consumer and automotive systems. Whether you need low leakage, high drive strength, or analog compatibility, our production-proven IP covers it all.

Frequently asked questions about GPIO Pad Library IP cores

What is TSMC N6 1.8V/3.3V Fail-Safe Fail-Tolerant SMBus?

TSMC N6 1.8V/3.3V Fail-Safe Fail-Tolerant SMBus is a GPIO IP core from Synopsys, Inc. listed on Semi IP Hub. It is listed with support for tsmc.

How should engineers evaluate this GPIO?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this GPIO IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP