3.3V Capable GPIO on TSMC 28nm RF HPC+
The 3.3V capable GPIO is an IP macro for on-chip integration.
Overview
The 3.3V capable GPIO is an IP macro for on-chip integration. It is a 3.3V general purpose I/O built with a stack of 1.8V thick oxide MOS devices. It is controlled by 0.9V (core) signals.
Supported features include core isolation, output enable and pull enable. Extra features such as input enable/disable, programmable drive strength and pull select, can be supported upon request.
By default, a 2kV HBM ESD protection is included. This is however easily scaled to any desired level. This specific IP macro is designed in TSMC 28nm RF HPC+ MMWave, and can be ported to other technologies upon request using inhouse design tool flow.
Key features
- Overvoltage tolerant design
- Deep N-Well
- DFM rules for manufacturing
- Core domain isolation
- Compatible with TSMC I/O ring
- Horizontal orientation
- Temp range -40°C to 125°C TJ
- 50kΩ pullup/pulldown
- Integrated 2kV HBM ESD
- 0.9V digital interface at the core side
- Bias generation circuit can be shared over multiple I/O instances
Block Diagram
Files
Note: some files may require an NDA depending on provider policy.
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 28nm | 28nm 280 nm | — |
Specifications
Identity
Provider
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Frequently asked questions about GPIO Pad Library IP cores
What is 3.3V Capable GPIO on TSMC 28nm RF HPC+?
3.3V Capable GPIO on TSMC 28nm RF HPC+ is a GPIO IP core from Sofics listed on Semi IP Hub. It is listed with support for tsmc.
How should engineers evaluate this GPIO?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this GPIO IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.