Vendor: Cadence Design Systems, Inc. Category: Coherency

Simulation VIP for AMBA CHI

Best-in-class Arm® AMBA® CHI Verification IP (VIP) for your IP, SoC, and System-level Design Testing Cadence provides a mature an…

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Overview

Best-in-class Arm® AMBA® CHI Verification IP (VIP) for your IP, SoC, and System-level Design Testing

Cadence provides a mature and comprehensive Verification IP (VIP) for the Coherent Hub Interface (CHI) specification, which is part of the Arm® AMBA® family of protocols. Incorporating the latest protocol updates, the Cadence Verification IP for CHI provides a complete bus functional model (BFM), integrated automatic protocol checks, and a coverage model. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for CHI provides a highly capable compliance verification solution that supports simulation, formal analysis, and hardware acceleration platforms. Cadence provides an integrated solution for interconnect verification, which supports the verification of coherent interconnect and performance analysis that provides automated generation of testbenches. The VIP runs on all major simulators and supports SystemVerilog and e verification languages, along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

Key Features

The table below shows the key features from the specifications implemented in the VIP:

Feature Name Description
Transaction type
  • Monitoring and driving of all protocol Opcodes
Dummy interconnect
  • Dummy CHI-based interconnect support. When interconnect is not present, the active Hn-F can generate snoop requests and respond to Rn-F commands
Communication layers
  • Link, network, and protocol-layer communication
Interface
  • Rn-F, Rn-D, Rn-I to Hn-F, Hn-D, Hn-I, Mn and Hn-F, Hn-I, Mn to Sn-F, Sn-I
Flow control
  • Flow control mechanisms support available across all RnX-to-HnX and HnX-to-SnX links
Channel delay
  • User can control the timing of individual flits
Cache model
  • Facilitates the role of actual L2 cache used in a CHI Rn-F
Cache access
  • Supports cache backdoor access as specific or random values can be sent to the cache at the beginning of a test or during run time
CHI-B
  • Monitoring and driving atomic transactions
  • Monitoring and driving stashing transactions
  • Support for Direct Memory Transfer (DMT) and Direct Cache Transfer (DCT)
  • Monitoring and driving de-allocating transactions
  • Optional addition of data check and poison
  • System coherency interface, used to connect and disconnect from a coherency domain
CHI-C
  • Monitoring and driving separate read data and home response
  • Monitoring and driving combined CompAck and write data
CHI-D
  • Supports monitoring and driving persistent CMO with two-part response
  • Support for Memory Partitioning and Monitoring (MPAM) feature
CHI-E
  • Memory tagging
CHI-F
  • Realm management extension
  • Page-based hardware attributes
CHI-G
  • Memory Encryption Contexts (MEC)
  • Device Assignment (DA)/Coherent Device Assignment (CDA)
  • Limited data elision
CHI-H
  • RME - Granular Data Isolation (GDI)
  • CMO to Point of Physical Storage (PoPS)
  • Multi-request
  • Resource Planes
  • Cache placement hint updates
Waveform Debugger
  • All the channel states are visible through the Waveform Debugger (Debug Useful technique)

Support Specification

  • AMBA 5 CHI A, B, C, D, E, F, G and H

 

Block Diagram

Simulation VIP for AMBA CHI block diagram

Benefits

  • Support testbench language interfaces for SystemVerilog, UVM, OVM, e, and SystemC
  • Generates constrained-random bus traffic with predefined error injection
  • Callbacks access at multiple queue points for scoreboarding and data manipulation
  • Provides comprehensive checking and coverage model
  • Includes embedded memory model in SN models
  • Includes embedded cache model in RN-F models
  • Packet tracker for ease of debugging
  • Seamless integration with System Verification Scoreboard (SVD) and System Performance Analyzer (SPA)

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
Simulation VIP for AMBA CHI
Vendor
Cadence Design Systems, Inc.

Provider

Cadence Design Systems, Inc.
HQ: USA
If you want to achieve silicon success, let Cadence help you choose the right IP solution and capture its full value in your SoC design. Cadence® IP solutions offer the combined advantages of a high-quality portfolio, an open platform, a modern IP factory approach to quality, and a strong ecosystem. Now you can tackle IP-to-SoC development in a system context, focus your internal effort on differentiation, and leverage multi-function cores to do more, faster. The Cadence IP Portfolio includes silicon-proven Tensilica® IP cores, analog PHY interfaces, standards-based IP cores, verification IP cores, and other solutions as well as customization services for current and emerging industry standards. The Cadence IP Factory provides you with an automated approach to the customization, delivery, and verification of SoC IP. As a result, you can spend more time on differentiation, with the assurance that you'll meet your performance, power, and area requirements. Choosing Cadence IP enables you to design with confidence because you have more freedom to innovate your SoCs with less risk and faster time to market.
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Learn more about Coherency IP core

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Co-Designed Cache Coherency Architecture for Embedded Multicore Systems

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Frequently asked questions about Coherency Interconnect IP cores

What is Simulation VIP for AMBA CHI?

Simulation VIP for AMBA CHI is a Coherency IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.

How should engineers evaluate this Coherency?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Coherency IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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