Vendor: Synopsys, Inc. Category: Coherency

Verification IP for Arm AMBA CHI Protocol

Synopsys Verification IP (VIP) for Arm® AMBA® CHI provides a comprehensive set of protocol, methodology, verification and product…

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Overview

Synopsys Verification IP (VIP) for Arm® AMBA® CHI provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve accelerated verification closure of Issue A/B/C/D/E/F/G based interconnects and interfaces. AMBA CHI VIP works in conjunction with other Synopsys AMBA VIP to provide a complete system solution for AMBA based designs.

AMBA CHI Verification

System Environment 
The Synopsys CHI VIP simulates CHI transactions through active agents, as defined by the CHI specification. The VIP provides a CHI System Environment (Env) which comprises of agents for RN (Request Node) and SN (Secondary Node), and a CHI System Monitor. The RN and SN agents support all the protocol features as per the CHI Specification and the methodology functionality normally associated with active and passive UVM components. The RN agent has an internal cache model which facilitates the sole of actual cache and the SN agent has an inbuilt memory instance.

The CHI System Environment itself is contained within top level System VIP component AMBA System Environment. UserS can either use AMBA System Env, CHI System Env, or standalone RN and SN agents in the testbench. The CHI System Monitor component is instantiated within the CHI System Env component. The System Monitor performs system-level checks across the CHI RN and SN ports within the system to ensure coherency is maintained as per the protocol.

AMBA Verification System Environment
The AMBA CHI verification system environment is integrated with the AMBA verification system environment to provide all of the configurability of the AMBA CHI Verification System Environment with the addition of AMBA 4 AXI, ACE, AHB and APB verification system environments. A system monitor provides system-wide checking across all of the protocols.

Key features

  • AMBA 5 CHI-A/B/C/D/E/F/G
  • Request node, secondary node agents and monitor
  • Complete port-level checks
  • Supports all interface types
  • AMBA CHI system monitor provides system-wide coherency and data integrity checks
  • AMBA CHI system environment encapsulates CHI primariy, secondary, monitors, interconnect environment
  • AMBA system environment encapsulates CHI and other AMBA protocols
  • VC SoC AutoTestBench helps in improving productivity by automatically generating SV UVM testbench reading DUT information

Block Diagram

Verification IP for Arm AMBA CHI Protocol block diagram

Files

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Specifications

Identity

Part Number
Verification IP for Arm AMBA CHI Protocol
Vendor
Synopsys, Inc.

Provider

Synopsys, Inc.
HQ: USA
Synopsys is a leading provider of high-quality, silicon-proven semiconductor IP solutions for SoC designs. The broad Synopsys IP portfolio includes logic libraries, embedded memories, analog IP, wired and wireless interface IP, security IP, embedded processors and subsystems. To accelerate IP integration, software development, and silicon bring-up, Synopsys’ IP Accelerated initiative provides architecture design expertise, pre-verified and customizable IP subsystems, hardening, and signal/power integrity analysis. Synopsys' extensive investment in IP quality, comprehensive technical support and robust IP development methodology enables designers to reduce integration risk and accelerate time-to-market.
Contact Synopsys, Inc.

Learn more about Coherency IP core

SoC design: When a network-on-chip meets cache coherency

Many people have heard the term cache coherency without fully understanding the considerations in the context of system-on-chip (SoC) devices, especially those using a network-on-chip (NoC). To understand the issues at hand, it’s first necessary to understand the role of cache in the memory hierarchy.

Co-Designed Cache Coherency Architecture for Embedded Multicore Systems

In this paper, we present the round-robin method applied to baseline coherency protocol and initial analysis of one hybrid protocol that performs speculative requests when access patterns are detected. We also propose to manage patterns through a dedicated hardware component attached to each core of the processor.

Frequently asked questions about Coherency Interconnect IP cores

What is Verification IP for Arm AMBA CHI Protocol?

Verification IP for Arm AMBA CHI Protocol is a Coherency IP core from Synopsys, Inc. listed on Semi IP Hub.

How should engineers evaluate this Coherency?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Coherency IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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