AMBA 4 ACE Verification IP
The AMBA® 4 ACE™ Verification IP provides an effective & efficient way to verify the components interfacing with ACE interface of…
Overview
The AMBA® 4 ACE™ Verification IP provides an effective & efficient way to verify the components interfacing with ACE interface of an IP or SoC. The AMBA® 4 ACE™ VIP is fully compliant with ACE specifications from ARM IHI 0022E ID022613. This is a light weight VIP with easy plugand-play interface so that there is no hit on the design cycle time.
Key features
- Fully compliant to the AMBA® 4 ACE™ Specification.
- Support for all type of AMBA 4 ACE devices.
- Rich set of configuration parameters to control ACE functionality.
- Parametrized bus width and cache line size.
- Interconnect model ensures that the interaction between all bus components is correct and follows the ACE protocol.
- Response comparison for all response channels.
- Supports optional Snoop Data channel.
- Supports Cache Maintenance transactions.
- Support to configure read/write transaction priority to the same address, issued at the same time.
- Capability of interconnect to modify a transaction.
- Supports sequencing of transactions for transactions occurring at approximately the same time to the same cache line.
- Support for Barrier transactions.
- Configurable modes for Valid and Ready signals on different channels.
- Support for Speculative read.
- Comprehensive Test Suites support constrained randomization and error injection.
- Supports advanced System Verilog features like constrained random testing.
- Supports dynamically configurable modes.
- Strong Protocol Monitor with real time exhaustive programmable checks.
- Supports Dynamic as well as Static Error Injection scenarios.
- On the fly protocol checking using protocol check functions, static and dynamic assertion.
- Built in Extensive Coverage Across the Channels.
- Provides a comprehensive user API (callbacks) for each component to override actual behaviour of component e.g. overriding write data from Master.
- Graphical analyser to show transactions for easy debugging.
Block Diagram
Benefits
- Available in native SystemVerilog (UVM/OVM/VMM) and Verilog
- Unique development methodology to ensure highest levels of quality
- Availability of various Regression Test Suites
- 24X5 customer support
- Unique and customizable licensing models
- Exhaustive set of assertions and cover points with connectivity example for all the components
- Consistency of interface, installation, operation and documentation across all our VIPs
- Provide complete solution and easy integration in IP and SoC environment
What’s Included?
- AMBA4 ACE Master/Slave Agent
- AMBA4 ACE Bus Monitor and Scoreboard across all interface (Optional)
- AMBA 4 ACE Interconnect Model (Optional)
- Test Environment & Test Suite :
- Basic and Directed Protocol Tests
- Random Tests
- Error Scenario Tests
- Assertions & Coverage Tests
- Integration Guide, User Manual and Release Notes
Files
Note: some files may require an NDA depending on provider policy.
Specifications
Identity
Provider
- To create world class Verification IP Solutions
- To provide expert consultancy to ASIC & SoC Design companies
- To design SOCs from Architecture to Working Silicon
- To be the leading provider of Semiconductor IP Solutions
- To be a one-stop-shop for Design and Verification
- Customer Success
- Commitment to Quality
- Quality of Products
- Quality of Engineers
- Best in class Customer Support
- Ethics and Integrity
Learn more about Coherency IP core
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Frequently asked questions about Coherency Interconnect IP cores
What is AMBA 4 ACE Verification IP?
AMBA 4 ACE Verification IP is a Coherency IP core from Truechip Solutions listed on Semi IP Hub.
How should engineers evaluate this Coherency?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Coherency IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.