Vendor: SmartDV Technologies Category: Coherency

AMBA ACE4 Assertion IP

AMBA ACE4 Assertion IP provides an smart way to verify the ARM AMBA ACE4 component of a SOC or a ASIC.

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Overview

AMBA ACE4 Assertion IP provides an smart way to verify the ARM AMBA ACE4 component of a SOC or a ASIC. The SmartDV's AMBA ACE4 Assertion IP is fully compliant with standard AMBA ACE4 Specification and provides the following features.

AMBA ACE4 Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

AMBA ACE4 Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key features

  • Specification Compliance
    • Compliant with the latest ARM AMBA ACE4 Protocol Specification.
    • Supports all ACE4 data and address widths.
    • Supports all protocol transfer types, burst types, burst lengths, burst sizes and response types.
    • Separate address, data and response phases. Separate read, write and snoop channels.
    • Support for burst-based transactions with only start address issued.
    • Write strobe support.
    • Narrow transfer support.
    • Unaligned address access support.
    • Ability to issue multiple outstanding transactions.
    • Out of order transaction completion support.
    • Protected accesses with normal/privileged,secure/non-secure and data/instruction.
    • Ability to configure the width of all signals.
    • Support for bus inactivity detection and timeout.
    • Configurable WID signal enable support.
    • Read data interleaving support with programmable interleave depth and programmable interleave size per transaction to allow fixed and variable data interleaving in a transaction.
    • Atomic access support with normal access and exclusive access.
    • Longer bursts up to 256 beats.
    • Quality of Service signaling.
    • Multiple region interfaces.
    • User signaling support.
    • Ability to break longer bursts into multiple shorter bursts.
    • Supports unmapped region address accesses.
    • AWCACHE and ARCACHE Attributes.
    • ACE4 specific features
    • Supports functionality to verify ACE4 and Cache Coherent Interconnect functionality for cache.
    • Supports all ACE4 transaction types including Snoop, Evict, WriteEvict, Barrier and Distributed virtual memory (DVM) transactions.
    • Support for multiple outstanding ACE4 transactions.
    • Supports all write/read responses and snoop responses.
    • Support for cache model and snoop filtering
  • Assertion IP features
    • Assertion IP includes:
    • System Verilog assertions
    • System Verilog assumptions
    • System Verilog cover properties
    • Synthesizable Verilog Auxiliary code
    • Support Master mode, Slave mode, Monitor mode and Constraint mode.
    • Supports Simulation mode (stimulus from SmartDV ACE4 VIP) and Formal mode (stimulus from Formal tool).
    • Rich set of parameters to configure ACE4 Assertion IP functionality.

Block Diagram

AMBA ACE4 AIP block diagram

Benefits

  • Runs in every major formal and simulation environment.

What’s Included?

  • Detailed documentation of Assertion IP usage.
  • Documentation also contains User's Guide and Release notes.

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
AMBA ACE4 AIP
Vendor
SmartDV Technologies

Provider

SmartDV Technologies
HQ: India
At SmartDV Technologies™, we believe there’s a better way to approach semiconductor intellectual property (IP) for integrated circuits. We’ve been focused exclusively on IP since 2007—so whether you’re sourcing standards-based design IP for your next SoC, ASIC, or FPGA, or seeking verification solutions (VIP) to put your chip design through its paces, you’ll find SmartDV’s IP straightforward to integrate. By combining proprietary SmartCompiler™ technology with the knowledge of hundreds of expert engineers, SmartDV can customize IP to meet your unique design objectives: quickly, economically, and reliably. Don’t allow other suppliers to force onesize-fits-all cores into your chip design. Get the IP you need, tailored to your specifications, with SmartDV: IP Your Way.
Contact SmartDV Technologies

Learn more about Coherency IP core

SoC design: When a network-on-chip meets cache coherency

Many people have heard the term cache coherency without fully understanding the considerations in the context of system-on-chip (SoC) devices, especially those using a network-on-chip (NoC). To understand the issues at hand, it’s first necessary to understand the role of cache in the memory hierarchy.

Co-Designed Cache Coherency Architecture for Embedded Multicore Systems

In this paper, we present the round-robin method applied to baseline coherency protocol and initial analysis of one hybrid protocol that performs speculative requests when access patterns are detected. We also propose to manage patterns through a dedicated hardware component attached to each core of the processor.

Frequently asked questions about Coherency Interconnect IP cores

What is AMBA ACE4 Assertion IP?

AMBA ACE4 Assertion IP is a Coherency IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this Coherency?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Coherency IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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