Vendor: 1-VIA Category: Multi-Protocol PHY

SerDes

1-VIA’s ultra-high-speed and ultra-low-power PCIe Gen 3/4/5 SerDes technology is customizable to meet your requirements for a wid…

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Overview

1-VIA’s ultra-high-speed and ultra-low-power PCIe Gen 3/4/5 SerDes technology is customizable to meet your requirements for a wide array of diverse applications.

Our advanced mixed signal technology empowers the industry’s leading 32Gbps multi-protocol and enterprise class PCIe Gen 4/5 SerDes optimized for a wide range of applications.

Key features

  • High-speed SerDes with ultra-low-power consumption
  • Industry’s fastest die to die communications
  • Multiprotocol SerDes: HMC, PCIe, SATA, SAS, and USB and more
  • High lane count with multiple data rates supported
  • Smallest die area with 1-VIA’s novel architecture

Files

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Specifications

Identity

Part Number
SerDes
Vendor
1-VIA

Provider

1-VIA
HQ: UK
1-VIA are continuously developing state-of-the-art, high-speed and low-power transceivers targeting next-generation satellite, data centre, telecommunications and automotive markets. With some of the industry’s most skilled and experienced analog/mixed-signal IC designers onboard they have a combined experience of more than 100 years in cutting-edge silicon design of high-speed ADC, DAC and PLL.
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Learn more about Multi-Protocol PHY IP core

How a 16Gbps Multi-link, Multi-protocol SerDes PHY Can Transform Datacenter Connectivity

Increasingly, more of the focus on mobile has centered around cloud datacenters and the networking to get the data back and forth between these datacenters and the mobile device. Functions like voice recognition and mapping depend on the ability to split the functionality between the smartphone, for local processing like encryption and compression, and the back end, where a large number of servers can do the heavier lifting before returning the results.

One PHY, Zero Tradeoffs: Multi-Protocol PHY for Edge AI Interface Consolidation

The Cadence 10G multi-protocol PHY was architected to address this exact challenge. Designed to scale across multiple process nodes, it consolidates PCI Express (PCIe), USB, DisplayPort, Ethernet, and other interfaces into a single, compact, silicon-efficient block. What sets it apart is simultaneous multi-protocol support, which enables multiple data paths without duplicating hardware, requiring extra board connectors, or paying the area and power penalty of separate IP blocks.

Frequently asked questions about Multi-Protocol PHY IP cores

What is SerDes?

SerDes is a Multi-Protocol PHY IP core from 1-VIA listed on Semi IP Hub.

How should engineers evaluate this Multi-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Multi-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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