Vendor: Renesas Category: Multi-Protocol PHY

MIPI D-PHY and FPD-Link (LVDS) Combinational Transmitter for TSMC 22nm ULP

The Renesas MIPI D-PHY and FPD-Link (LVDS) combinational Transmitter is useful 4 Data Channel driver hard macro for DSI of TSMC 2…

TSMC 22nm ULP View all specifications

Overview

The Renesas MIPI D-PHY and FPD-Link (LVDS) combinational Transmitter is useful 4 Data Channel driver hard macro for DSI of TSMC 22nm ULP process.

Key features

  • Renesas MIPI D-PHY Transmitter can be used for analog Driverof following interface .
    • MIPI alliance Specification for D-PHY Version 2.1 15 December 2016.
    • MIPI alliance Specification for Display Serial Interface (DSI).
  • Renesas LVDS Transmittercan be used for analog Driver of following interface.
    • FPD-Link(LVDS) Specification for Version D-PHY ANSI/TIA/EIA-644-A FEBRUARY 2001.
  • Technology is TSMC 22nm ULP 1p10M.
  • Supply voltage can be applied 1.0V for core voltage, 1.8V  for IO voltage.
  • Maximum data rate of each channel is 1.5Gbps at High-speed mode for MIPI D-PHY Transmitter.
  • Data rate of each channel is 609Mbps for FPD-Link(LVDS).

Block Diagram

Files

Note: some files may require an NDA depending on provider policy.

Silicon Options

Foundry Node Process Maturity
TSMC 22nm ULP

Specifications

Identity

Part Number
MIPI D-PHY: Transmitter for DSI with FPD-Link TX
Vendor
Renesas

Provider

Renesas
HQ: Japan
Renesas Electronics Corporation (TSE: 6723), a premier supplier of advanced semiconductor solutions, today announced it is expanding access to its extensive portfolio of intellectual property (IP) licenses that allow designers to meet a broad range of customized customer requirements in a rapidly changing industry. Renesas has incorporated a broad range of IP into its microcontrollers (MCUs) and system on chip (SoC) products spans, including central processing unit (CPU) IP, communication interface IP, timer IP, memory IP, and analog IP. Effective today, Renesas is offering customers access to the most highly sought assets from its IP portfolio. The first batch of offerings will consist of over 40 licenses, including CPU cores (RX, SH, etc.), timer IP for motor applications, USB cores, and SRAM. More licenses will be offered moving forward in response to demand.

Learn more about Multi-Protocol PHY IP core

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One PHY, Zero Tradeoffs: Multi-Protocol PHY for Edge AI Interface Consolidation

The Cadence 10G multi-protocol PHY was architected to address this exact challenge. Designed to scale across multiple process nodes, it consolidates PCI Express (PCIe), USB, DisplayPort, Ethernet, and other interfaces into a single, compact, silicon-efficient block. What sets it apart is simultaneous multi-protocol support, which enables multiple data paths without duplicating hardware, requiring extra board connectors, or paying the area and power penalty of separate IP blocks.

Frequently asked questions about Multi-Protocol PHY IP cores

What is MIPI D-PHY and FPD-Link (LVDS) Combinational Transmitter for TSMC 22nm ULP?

MIPI D-PHY and FPD-Link (LVDS) Combinational Transmitter for TSMC 22nm ULP is a Multi-Protocol PHY IP core from Renesas listed on Semi IP Hub. It is listed with support for tsmc.

How should engineers evaluate this Multi-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Multi-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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