Vendor: Qualitas Semiconductor Category: Multi-Protocol PHY

100G SerDes PAM4 PHY

The SERDES PHY IP delivers a high-performance, low-power solution for high-speed interfaces up to 112Gbps.

Overview

The SERDES PHY IP delivers a high-performance, low-power solution for high-speed interfaces up to 112Gbps. It supports diverse applications including AI accelerators, data centers, 5G infrastructure, and automotive SoCs.

The Ethernet PHY IP is optimized for CEI-112G and supports 8b/10b encoding for Gen1/Gen2 and 128b/130b for Gen3/Gen4, ensuring accurate serialization and deserialization of data streams.

With robust equalization and proven interoperability, it maintains high signal integrity across lossy channels and is well-suited for advanced SoC integration.

Key features

  • Transmit Path:
    • Accepts four 10-bit transmit characters (8b/10b) or four 8-bit data blocks (128b/130b)
    • Serializes data to differential outputs (TXP/TXN) at up to 16.0Gb/s per lane
  • Receive Path:
    • Samples incoming serial data from differential inputs (RXP/RXN)
    • Deserializes into four 10-bit (8b/10b) or 8-bit (128b/130b) received characters
  • Optimized for high-speed Ethernet, PCIe, and custom protocol applications
  • Integrated with robust equalization and low-jitter clock recovery for enhanced signal integrity

Block Diagram

Files

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Specifications

Identity

Part Number
100G SerDes PAM4 PHY
Vendor
Qualitas Semiconductor

Provider

Qualitas Semiconductor
HQ: South Korea
Qualitas Semiconductor is a leader in high-speed interconnect technology, which is at key infrastructure of the 4th Industrial Revolution, Encompassing AI, mobile devices, automotive systems, and displays. We specialize in high-speed interconnect circuit design, as well as ultra-fine semiconductor process design and verification. We operate our business through the licensing of high-speed interface IP and by providing comprehensive design services. Moreover, we have established a robust design methodology to ensure high-reliability in ultra-fine semiconductor processes. With a proven track record in developing and mass-producing cutting-edge semiconductors, our expertise spans the most advanced technologies.

Learn more about Multi-Protocol PHY IP core

How a 16Gbps Multi-link, Multi-protocol SerDes PHY Can Transform Datacenter Connectivity

Increasingly, more of the focus on mobile has centered around cloud datacenters and the networking to get the data back and forth between these datacenters and the mobile device. Functions like voice recognition and mapping depend on the ability to split the functionality between the smartphone, for local processing like encryption and compression, and the back end, where a large number of servers can do the heavier lifting before returning the results.

One PHY, Zero Tradeoffs: Multi-Protocol PHY for Edge AI Interface Consolidation

The Cadence 10G multi-protocol PHY was architected to address this exact challenge. Designed to scale across multiple process nodes, it consolidates PCI Express (PCIe), USB, DisplayPort, Ethernet, and other interfaces into a single, compact, silicon-efficient block. What sets it apart is simultaneous multi-protocol support, which enables multiple data paths without duplicating hardware, requiring extra board connectors, or paying the area and power penalty of separate IP blocks.

Frequently asked questions about Multi-Protocol PHY IP cores

What is 100G SerDes PAM4 PHY?

100G SerDes PAM4 PHY is a Multi-Protocol PHY IP core from Qualitas Semiconductor listed on Semi IP Hub.

How should engineers evaluate this Multi-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Multi-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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