Vendor: Certus Semiconductor Category: Multi-Protocol PHY

32Gbps SerDes PHY in GF 22nm

A 32Gbps SerDes PHY in GlobalFoundries 22FDX withlow-jitter, half-rate tran mission, and a configurable CTLE-based receiver.

GlobalFoundries 22nm FDX View all specifications

Overview

A 32Gbps SerDes PHY in GlobalFoundries 22FDX withlow-jitter, half-rate tran mission, and a configurable CTLE-based receiver.

This 32Gbps SerDes PHY is implemented in GlobalFoundries 22FDX CMOS technology and provides a high-performance, protocol-agnostic serial interface for advanced mixed-signal and high-speed digital SoCs. The PHY is architected as a modular design consisting of a low-jitter clock multiplier, a half-rate transmitter with digitally programmable feed-forward equalization, and a configurable CTLE-based receiver with digital clock-and-data recovery, supporting both 16 Gbps and 32 Gbps operation. The design emphasizes observability and manual configurability, exposing trim controls and monitoring capabilities to support bring-up, characterization, and production test. The SerDes is optimized for integration in GF 22FDX using 0.8V core devices and a high-performance BEOL stack. The design is currently in pre-silicon validation, with tapeout planned.

Library Summary

  • Process: GlobalFoundries 22FDX
  • BEOL: 1P9M_2Mx_5Cx_1Jx_1Ox_LB
  • PDK: GF 22FDX-EXT
  • Clocking: On-chip clock multiplier for 8 GHz-> 16 GHz operation
  • TX Interface: 16-bit parallel input-> differential serial output
  • RX Interface: Differential serial input-> 16-bit parallel output (word clock provided)
  • Equalization: TX 3-tap FFE (pre/main/post); RX CTLE with DC + HF gain controls

Operating Conditions

Parameter Value
Line Rate 16Gbps / 32Gbps (per lane)
Reference Clock 8 Ghz differential reference
Core VDD 0.8V (0.72V-0.88V)
RX Analog Supply 1.8V (receiver analog rail)
Signaling Differential CML at pads (TX)

 

 

Key features

  • Upto 32Gbps per lane with 16Gbps support
  • Half-rate TX architecture to reduce internal clock fre quency while maintaining throughput
  • Configurable RX CTLE with independent DC gain and HF peaking control
  • Digital CDR with configurable loop parameters
  • Observability fo bring-up and production
  • Protocol-agnostic PHY suitable for a range of serial link implementations

Block Diagram

Applications

  • High-speeddataconverter interfaces (e.g. JESD204B/C style links)
  • Radar, defense, and real-time signal processing back planes
  • Test measurementandhigh-speedinstrumentation links
  • Proprietary chip-on-chip / module-to-module serial in terconnects

Files

Note: some files may require an NDA depending on provider policy.

Silicon Options

Foundry Node Process Maturity
GlobalFoundries 22nm FDX

Specifications

Identity

Part Number
DS22
Vendor
Certus Semiconductor

Provider

Certus Semiconductor
HQ: United States
Certus Semiconductor has assembled several of the world’s foremost experts in IO and ESD design to offer our clients the ability to affordably tailor their IO libraries into the optimal fit for their products. Certus is offering the semiconductor industry a unique approach to custom IO libraries, including tailored IO designs, and ESD solutions based on simulations leveraging specialized silicon ESD models. In addition to offering fast turnaround custom IO designs, Certus offers independent ESD design, review and debug services. Through partnerships, Certus is also able to provide ESD testing & TLP support.

Learn more about Multi-Protocol PHY IP core

How a 16Gbps Multi-link, Multi-protocol SerDes PHY Can Transform Datacenter Connectivity

Increasingly, more of the focus on mobile has centered around cloud datacenters and the networking to get the data back and forth between these datacenters and the mobile device. Functions like voice recognition and mapping depend on the ability to split the functionality between the smartphone, for local processing like encryption and compression, and the back end, where a large number of servers can do the heavier lifting before returning the results.

One PHY, Zero Tradeoffs: Multi-Protocol PHY for Edge AI Interface Consolidation

The Cadence 10G multi-protocol PHY was architected to address this exact challenge. Designed to scale across multiple process nodes, it consolidates PCI Express (PCIe), USB, DisplayPort, Ethernet, and other interfaces into a single, compact, silicon-efficient block. What sets it apart is simultaneous multi-protocol support, which enables multiple data paths without duplicating hardware, requiring extra board connectors, or paying the area and power penalty of separate IP blocks.

Frequently asked questions about Multi-Protocol PHY IP cores

What is 32Gbps SerDes PHY in GF 22nm?

32Gbps SerDes PHY in GF 22nm is a Multi-Protocol PHY IP core from Certus Semiconductor listed on Semi IP Hub. It is listed with support for globalfoundries.

How should engineers evaluate this Multi-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Multi-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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