Vendor: SmartDV Technologies Category: UART

MIPI DEBUG UART Verification IP

MIPI_DEBUG_UART Verification IP provides an smart way to verify the MIPI_DEBUG_UART component of a SOC or a ASIC.

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Overview

MIPI_DEBUG_UART Verification IP provides an smart way to verify the MIPI_DEBUG_UART component of a SOC or a ASIC. The SmartDV's MIPI_DEBUG_UART Verification IP is fully compliant with MIPI_DEBUG_UART DDI0183G_uart_pl011_r1p5_trm Specification and provides the following features.

MIPI_DEBUG_UART Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

MIPI_DEBUG_UART Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key features

  • APB common support
    • Supports different transfer types including IDLE, WRITE and READ.
    • Supports unaligned address accesses.
    • Slave memory map support.
    • Supports Unmapped address accesses.
    • Programmable number of idle cycles
    • Ability to inject errors during data transfer.
    • Supports FIFO memory.
  • Transmit and receive commands allow the user to transmit and receive data.
  • Supports character width from 1 bit to 32 bits.
  • Configurable receive FIFO depth.
  • Supports constraints Randomization.
  • Callbacks in transmitter, receiver and monitor for user processing of data.
  • On-the-fly protocol and data checking.
  • Ability to transmit strings to help verification of SOC.
  • Notifies the testbench of significant events such as transactions, warnings, and protocol violations.
  • UART Adaptor Verification IP comes with complete testsuite to verify each and every feature of UART Adaptor specification.

Block Diagram

MIPI DEBUG UART VIP block diagram

Benefits

  • Faster testbench development and more complete verification of designs.
  • Easy to use command interface simplifies test bench control and configuration of master and slave.
  • Simplifies results analysis.
  • Integrates easily into Open Vera, System Verilog, and Verilog.
  • Runs in every major simulation environment.

What’s Included?

  • Complete regression suite containing all the MIPI_DEBUG_UART testcases.
  • Examples showing how to connect various components, and usage of BFM and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation contains User's Guide and Release notes.

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
MIPI DEBUG UART VIP
Vendor
SmartDV Technologies

Provider

SmartDV Technologies
HQ: India
At SmartDV Technologies™, we believe there’s a better way to approach semiconductor intellectual property (IP) for integrated circuits. We’ve been focused exclusively on IP since 2007—so whether you’re sourcing standards-based design IP for your next SoC, ASIC, or FPGA, or seeking verification solutions (VIP) to put your chip design through its paces, you’ll find SmartDV’s IP straightforward to integrate. By combining proprietary SmartCompiler™ technology with the knowledge of hundreds of expert engineers, SmartDV can customize IP to meet your unique design objectives: quickly, economically, and reliably. Don’t allow other suppliers to force onesize-fits-all cores into your chip design. Get the IP you need, tailored to your specifications, with SmartDV: IP Your Way.
Contact SmartDV Technologies

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Frequently asked questions about UART IP cores

What is MIPI DEBUG UART Verification IP?

MIPI DEBUG UART Verification IP is a UART IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this UART?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this UART IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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