Vendor: Chip Interfaces ApS Category: JESD204

JESD204B Controller IP

Industry , Silicon Proven, 16 Gbps per lane IP core, backed by a portfolio of verification tools, PHY interop, and hardware demos…

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Overview

Industry Leading, Silicon Proven, 16 Gbps per lane IP core, backed by a complete portfolio of verification tools, PHY interop, and hardware demos

The JESD204B controller IP is a highly optimized and silicon agnostic implementation of the JEDEC JESD204B.01 serial interface standard targeting both ASICs and FPGAs. The solution by default provides line-speeds of up to 12.5 Gbps per lane while guaranteeing data alignment and synchronization. The standard allows it to optionally by used up to 16 Gbps, but does not recommend running it faster due to the 8b 10b encoding.

The core enables quick and reliable deployment of both the transmitter (TX) and the receiver (RX) and comes optionally with a tightly integrated transport layer option, that can dynamically be configured to handle any Multiple-Converter Device Alignment, Multiple Lanes (MCDA-ML) requirements.

The IP comes with the widest parameter set available and has gone through extensive testing. The IP core is silicon proven, heavily tested in UVM regression environment and has been interoperability tested with key Data Converter ADC/DAC providers and leading SerDes PHY solutions.

JESD204B delivers all the features of the standard. The solution includes separate RX, TX modules containing the link layer and transport layer.

Gearboxes are included to enable easy interfacing to any SERDES width. Chip Interfaces JESD204 IP design can include Link Layers from B, C and D versions of the standard making the final solution more flexible and compatible with more devices. 

The IP is interoperability tested with leading PHY and data convertor vendors, Silicon proven across all major fabrication nodes and plants, and regression tested to 100% coverage.

Key features

  • Designed to JEDEC JESD204B.01 specification
  • Line rates from 1 Gbps to 12.5 Gbps (with optional extension to 16 Gbps)
  • Supports 1-24 lanes
  • Supports 1-96 converters
  • HD-mode supported
  • Performs user-enabled scrambling
  • Generates initial lane alignment sequence (ILAS)
  • Performs the alignment character generation
  • Checks link configuration data with user selected parameter values during ILAS
  • 8b 10b encoding
  • Transport layer data mapping and de-mapping
  • Supports Subclasses (0, 1, and 2)

Block Diagram

JESD204B block diagram

What’s Included?

  • The IP Core can be delivered in Source code or Encrypted format.
  • The following deliverables will be provided with the IP Core license:
    • Solid documentation, including User Manual, Release Note and Quick Start Guide.
    • Simulation Environment, including Simple Testbed, Test case, Test Script.
    • Timing Constraints in Synopsys SDC format.
    • Access to support system and direct support from Chip Interfaces Engineers.
    • Test Report , Synopsys SGDC Files and Synopsys Lint, CDC and Waivers available on request

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
JESD204B
Vendor
Chip Interfaces ApS

Provider

Chip Interfaces ApS
HQ: Denmark
Chip Interfaces is your trusted partner for digital high-performance IP cores that meet the demanding requirements of next-generation applications. With a proven track record of delivering cutting-edge IP solutions, Chip Interfaces is a partner you can trust for your next project. We consider ourselves at the forefront of innovation, empowering chip designers to achieve exceptional performance and reliability, through significant investments in next generation technologies. Our wide range of digital IP cores encompasses JESD204, MIPI, Interlaken, CPRI/eCPRI, and RSFECs. Chip Interfaces silicon-agnostic and customizable IPs are interoperability tested with leading PHY providers, verified using the latest UVM regression techniques, and validated in test beds to ensure seamless integration with a wide range of other components and hardware platforms. This commitment to interoperability, verification and validation simplifies the design process and minimizes the risk of integration issues and ensures quality. We provide comprehensive support throughout the entire IP implementation process, and Chip Interfaces offers direct support from the engineers who designed and developed the IP cores. This unparalleled access to IP experts ensures timely and accurate guidance, enabling faster time to market. Our commitment to quality and excellence, coupled with our true wish to make our customers succeed, positions us as a trusted partner for your next project.
Contact Chip Interfaces ApS

Learn more about JESD204 IP core

JESD204 Frame Mapping explained from converter samples to lanes

The JESD204 Transport Layer oversees converter data mapping onto a set of JESD204 Lanes. The nature of these lanes is dependent on the version of the JESD204 standard and a function of the PCS and over the years despite the Serdes technology changing with ever increasing line rates, the function and features of the Transport Layer remained the same

Multiple ways JESD204 performs bitstream alignment

Bitstream alignment is a function of the Receiver (RX), as seen in the figure below it is the first functional block of the receiver right after the clock domain crossing (CDC) and gear boxing which are quite generic Serdes adaptation layer that can be found in almost every design working with a Serdes.

Frequently asked questions about JESD204 IP cores

What is JESD204B Controller IP?

JESD204B Controller IP is a JESD204 IP core from Chip Interfaces ApS listed on Semi IP Hub.

How should engineers evaluate this JESD204?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this JESD204 IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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