Vendor: MTI Mobile Category: JESD204

JESD204B Controller

JESD204B is a JEDEC interfacing standard for high-speed serial communications of digital radio samples and control data between l…

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Overview

JESD204B is a JEDEC interfacing standard for high-speed serial communications of digital radio samples and control data between latest generation of data converters (DACs and ADCs) and Digital Signal Processing (DSP) devices implemented generally by FPGA / ASSP / ASICs targets. MTI’s IPC-JESD204B controller solution enables the quickest and most reliable deployment of both the Transmitter (TX) and Receiver (RX) controller modules for flexible and high perfomance data transfers up to 12.5 Gbps (depending on silicon technology target) per lane in compliance with the latest JESD204B.01 2012 standard release. It includes all main features required to support MCDA-ML applications. MTI’s IPC-JESD204B is a self-contained, fully tested and third party interoperable solution widely used today in a number of Tier1 applications for ASIC/ASSP and FPGAs devices.

Key features

  • Standard version: JESD204B 2012
  • Versions Available: Transmitter / Receiver
  • Applications and Technologies Supported: ASIC, ASSP, FPGA in VHDL-93 RTL
  • Line rates: 12.5 Gbps
  • Modes: Modes ML / SL
  • HD Mode: Supported
  • Lanes:1 to 8
  • Converters: 1 to 8
  • Mapping Interface: 64 bits * NO_CONVERTERS
  • Sample widths: N = 12, 14, 15 ,16 bits
  • Data Scrambling: Supported
  • 8b10b coding: Supported
  • Device Type: MCDA-ML
  • Configuration and Status: 32bits CPU interface
  • Mandatory Test Cases: Supported
  • Deterministic Latency: ClassI
  • Backward compatibility: Class0

Benefits

  • High Throughput: Enables up to 12.5 Gbps lane speeds in compliance with JESD204B.01.
  • High Flexibility: Enables programmable number of converters modules (M) and lanes (L). Supports variable sample width size from 12 to 16 bits at run-time, High Density (HD) mode, multi-lane alignment. Deterministic Latency Class1 support with SYSREF. Backward compatibility with Class 0 devices is also supported.
  • Multi-application: Supports a wide range of applications including medical imaging, wireless base stations and generic data communications.
  • Portable :Designed in generic VHDL-93 and targeting any RTL implementation like ASICs, ASSPs and FPGAs.
  • Deterministic Latency:Enables very accurate knowledge of internal delays required by advanced signal processing techniques based on delay-awareness (MIMO/Beamforming) and in compliance with JESD204B.01 2012 Sub-Class I deterministic latency requirements.

Applications

  • Supports a wide range of applications including ultrasound, medical imaging, wireless base stations and generic data communications.

What’s Included?

  • User Manual
  • Vertification Guide
  • Test Environment for Simulation
  • Test Cases
  • IPC Block (encrypted source code or netlist)
  • FPGA Hardware Test Bed (optional)

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
IPC-JESD204-B
Vendor
MTI Mobile

Provider

MTI Mobile
HQ: Denmark
Microelectronics Technology Inc. (MTI) Mobile is a leading global provider of products and solutions for the wireless telecommunications industry, including mobile network and radio components for 2G, 3G and 4G networks. MTI Mobile develops its state-of-the-art radio and interfacing technology in Taiwan, Denmark and the USA while owning and operating manufacturing facilities in Taiwan and China.
Contact MTI Mobile

Learn more about JESD204 IP core

JESD204 Frame Mapping explained from converter samples to lanes

The JESD204 Transport Layer oversees converter data mapping onto a set of JESD204 Lanes. The nature of these lanes is dependent on the version of the JESD204 standard and a function of the PCS and over the years despite the Serdes technology changing with ever increasing line rates, the function and features of the Transport Layer remained the same

Multiple ways JESD204 performs bitstream alignment

Bitstream alignment is a function of the Receiver (RX), as seen in the figure below it is the first functional block of the receiver right after the clock domain crossing (CDC) and gear boxing which are quite generic Serdes adaptation layer that can be found in almost every design working with a Serdes.

Frequently asked questions about JESD204 IP cores

What is JESD204B Controller?

JESD204B Controller is a JESD204 IP core from MTI Mobile listed on Semi IP Hub.

How should engineers evaluate this JESD204?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this JESD204 IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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