Vendor: MAXVY Technologies Pvt Ltd Category: JESD204

JESD204B UVM VIP

The vendor provides configurable JESD204B TX/RX verification IP.

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Overview

The vendor provides configurable JESD204B TX/RX verification IP. JESD204B is a Serial Interface for Data Converters which are defined by JEDEC SOLID STATE TECHNOLOGY ASSOCIATION. Our VIP covers Transport and Data link layer functionality of JESD204B. The VIP provides more flexible configuration to user to select their needs like lane,device configuration, data width.

Key features

  • ADC - TX/RX DAC - TX/RX.
  • Support up to 12.5 Gbps data rate.
  • Support configurable device classification.
  • Support configurable subclass 0/1/2.
  • Support Frame alignment monitor and correction.
  • Support lane synchronization.
  • Support Lane alignment monitor and correction.
  • Support Link configuration.
  • Support Link re-initialization.
  • Support Deterministic Latency.
  • Support 8B/10B encode/decode.
  • Support Application specific control interface (user specific).

Block Diagram

JESD204B UVM VIP block diagram

Benefits

  • Configurable Option like lane,frame,TX/RX.
  • Supports both multi device configuration.
  • Simple steps to integrate into customer environment

What’s Included?

  • Basic Test Suite.
  • Random Testbench Environment.
  • Encrypted Source Code of VIP.
  • VIP user guide.

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
JESD204B UVM VIP
Vendor
MAXVY Technologies Pvt Ltd

Provider

MAXVY Technologies Pvt Ltd
HQ: India
MAXVY is a fast growing company which is currently engaged in the fields of Semiconductor. We offer our services to shape your concept to products (Silicon Chips), which includes Embedded Product Design, RTL design and Verification, Analog and Mixed Signal System Design and Analysis, Physical Design etc...
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Learn more about JESD204 IP core

JESD204 Frame Mapping explained from converter samples to lanes

The JESD204 Transport Layer oversees converter data mapping onto a set of JESD204 Lanes. The nature of these lanes is dependent on the version of the JESD204 standard and a function of the PCS and over the years despite the Serdes technology changing with ever increasing line rates, the function and features of the Transport Layer remained the same

Multiple ways JESD204 performs bitstream alignment

Bitstream alignment is a function of the Receiver (RX), as seen in the figure below it is the first functional block of the receiver right after the clock domain crossing (CDC) and gear boxing which are quite generic Serdes adaptation layer that can be found in almost every design working with a Serdes.

Frequently asked questions about JESD204 IP cores

What is JESD204B UVM VIP?

JESD204B UVM VIP is a JESD204 IP core from MAXVY Technologies Pvt Ltd listed on Semi IP Hub.

How should engineers evaluate this JESD204?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this JESD204 IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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