Vendor: SmartDV Technologies Category: JESD204

JESD207 Verification IP

The SmartDV's JESD207 verifies the Radio Front end-Baseband digital parallel interface.JESD207 Verification IP can be used to ver…

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Overview

The SmartDV's JESD207 verifies the Radio Front end-Baseband digital parallel interface.JESD207 Verification IP can be used to verify BBIC or RFIC following the JESD207 basic protocol as defined in JESD207 and provides the following features.

JESD207 Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

JESD207 Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key features

  • Supports JESD207 specification.
  • Operates as BBIC (Baseband IC) and RFIC (Radio front end IC) monitor.
  • Supports half duplex data transfer.
  • Supports DDR source synchronous data transfer timing.
  • Supports both data path transaction and control plane transactions.
  • Supports multiple parallel sample streams in BBIC and RFIC data path interface.
  • Supports data path transaction
    • Supports transmit burst and receive burst
    • Supports both 10 bits and 12 bits sample width
    • Supports 2 way interleave and 4 way interleave transactions
    • Supports 1T1R,1T2R,2T2R systems
  • Supports control plane transaction
    • Supports 4 wires write and 4 wires read
    • Supports 3 wires write and 3 wires read
    • 1bit command plus 7bit address control field format
    • Serial clock can be stopped between transactions for reducing control plane power consumption to negligible levels
    • Extended data tranactions
  • Supports various kinds of errors
    • Mixed data error
    • Invalid address error
  • Status counters for various events on bus.
  • Supports constraints randomization.
  • Built in functional coverage analysis.
  • Callbacks in BBIC and RFIC for various events.
  • Test suite to test each and every feature of JESD207 specification.

Block Diagram

JESD207 VIP block diagram

Benefits

  • Faster test bench development and more complete verification of JESD207 designs.
  • Simplifies results analysis.
  • Runs in every major simulation environment.
  • Easy to use command interface simplifies testbench control and configuration of BBIC and RFIC.
  • Comes with complete test suite to test each and every feature of JESD207.

What’s Included?

  • Complete regression suite containing all the JESD207 testcases.
  • Examples showing how to connect various components,and usage of BBIC,RFIC and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation contains User's Guide and Release notes.

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
JESD207 VIP
Vendor
SmartDV Technologies

Provider

SmartDV Technologies
HQ: India
At SmartDV Technologies™, we believe there’s a better way to approach semiconductor intellectual property (IP) for integrated circuits. We’ve been focused exclusively on IP since 2007—so whether you’re sourcing standards-based design IP for your next SoC, ASIC, or FPGA, or seeking verification solutions (VIP) to put your chip design through its paces, you’ll find SmartDV’s IP straightforward to integrate. By combining proprietary SmartCompiler™ technology with the knowledge of hundreds of expert engineers, SmartDV can customize IP to meet your unique design objectives: quickly, economically, and reliably. Don’t allow other suppliers to force onesize-fits-all cores into your chip design. Get the IP you need, tailored to your specifications, with SmartDV: IP Your Way.
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Learn more about JESD204 IP core

JESD204 Frame Mapping explained from converter samples to lanes

The JESD204 Transport Layer oversees converter data mapping onto a set of JESD204 Lanes. The nature of these lanes is dependent on the version of the JESD204 standard and a function of the PCS and over the years despite the Serdes technology changing with ever increasing line rates, the function and features of the Transport Layer remained the same

Multiple ways JESD204 performs bitstream alignment

Bitstream alignment is a function of the Receiver (RX), as seen in the figure below it is the first functional block of the receiver right after the clock domain crossing (CDC) and gear boxing which are quite generic Serdes adaptation layer that can be found in almost every design working with a Serdes.

Frequently asked questions about JESD204 IP cores

What is JESD207 Verification IP?

JESD207 Verification IP is a JESD204 IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this JESD204?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this JESD204 IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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