USB 2.0 OTG PHY IP, UMC 0.13um HS/FSG process
USB 2.0 On-The-Go PHY, UMC 0.13um HS/FSG Logic process.
- USB 2.0
- UMC
- 130nm
- HS
Single-Protocol PHY IP cores help engineering teams evaluate reusable semiconductor IP for advanced chip designs.
This page lets you compare Single-Protocol PHY IP offerings from multiple vendors based on functionality, integration requirements, performance targets, power efficiency, and process compatibility.
USB 2.0 OTG PHY IP, UMC 0.13um HS/FSG process
USB 2.0 On-The-Go PHY, UMC 0.13um HS/FSG Logic process.
USB 1.1.OTG PHY IP, OTG, UMC 0.13um SP/FSG process
USB 1.1 On-The-Go transceiver, UMC 0.13um SP/FSG Logic process.
USB 1.1 PHY IP, UMC 0.13um HS/FSG process
USB 1.1 PHY, UMC 0.13um HS/FSG Logic process.
SATA II PHY IP, Gen-2, UMC 0.13um HS/FSG process
Serial ATA (SATA) physical layer that provides a range of host and device functions, UMC 0.13um HS/FSG Logic process.
SATA II PHY IP, Support SATA Gen1 1.5Gb/s and SATA Gen2 3.0Gb/s, UMC 0.18um Logic process
Single channel serial ATA PHY layer compliant with SATA spec.
USB 1.1.OTG PHY IP, OTG, UMC 0.18um G2 process
USB 1.1 On-The-Go transceiver (ECN spec), UMC 0.18um GII Logic process.
IP
USB 1.1 PHY, Support Low Speed and Full Speed - HLMC 55nm
USB 1.1 PHY, Support Low Speed and Full Speed - HLMC 55nm
USB 1.1 PHY, Support Low Speed and Full Speed - HHGrace 110nm
USB 1.1 PHY, Support Low Speed and Full Speed - HHGrace 110nm
LVDS TX IP, 1Gbps for Per-Lane - SMIC 28nm
LVDS TX IP, 1Gbps for Per-Lane - SMIC 28nm
GLOBALFOUNDARIES 22nm FDSOI USB3.0 Dual Role PHY/OTG PHY
This USB3.0 PHY IP is designed according to USB3.0 and USB2.0 specification.
Receive the high speed serial signal, transfer it to parallel data and unpack the symbol packet, direct video stream output final…
The PCIe Gen3 PCS for 28nm programmable serdes.
The PCIe Gen3 PCS for 28nm programmable serdes.
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Crystal-free USB1.1 device PHY
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Crystal-less USB 1.1 Transceiver PHY
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Crystal-less USB1.1 device PHY total solution
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