HBM4 PHY IP

Synopsys offers a complete HBM4 PHY IP solution for high-performance computing (HPC), AI, graphics, and networking ASIC, Application-Specific Standard Product (ASSP), and SoC applications requiring high-bandwidth HBM4 DRAM interfaces operating at up to 12 Gbps per data pin. The Synopsys HBM4 PHY delivers superior power efficiency compared to other off-chip memory interface solutions and supports up to four active operating states for dynamic frequency scaling. To minimize area, the PHY uses an optimized micro bump array, and support for longer channel lengths allows greater flexibility in PHY placement on the SoC without impacting performance. Combined with Synopsys HBM4 Controller IP and HBM4 memory model VIP, the PHY provides a complete HBM4 interface solution. The Synopsys HBM4 PHY is provided as a hard PHY delivered as GDSII, which includes integrated application-specific HBM4 I/0s required for HBM4 signaling. The design is optimized for high performance, low latency, small area, low power, and ease of integration. The hard PHY is easily assembled into a complete 2048-bit HBM4 PHY. It consists of RTL-based PHY Utility Block (PUB) which includes PHY training circuitry, configuration registers, and BIST control. It features a DFI 5.1-compatible interface to the memory controller, supporting DFI 1:4:8 clock ratio, and includes metal-insulator-metal (MIM) power decoupling.

• Supports JEDEC HBM4 DRAMs
• Supports data rates up to 12 Gbps
• Supports up to 32 independent 64-bit memory channels
• Pseudo-channel operation supported to enable up to 64 32-bit pseudo-channels with 2048-bit PHY
• DFI 5.1-compatible controller interface
• At-speed loopback testing supported on both address and data channels
• Any information on trained frequencies? Four state frequencies
• IEEE 1500/lane repair  
• Supports MBIST
• Comprehensive set of design-for-test (DFT) features
• PHY optimized to improve interposer routing
• Access to in-house SIPI and interposer expertise to facilitate customer’s design activities