Vendor: SmartDV Technologies Category: Single-Protocol PHY

10G TBI (PCS) Ethernet Verification IP

The 10G TBI Ethernet Verification IP is compliant with IEEE 802.3 specifications and verifies MAC-to-PHY layer interfaces of desi…

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Overview

The 10G TBI Ethernet Verification IP is compliant with IEEE 802.3 specifications and verifies MAC-to-PHY layer interfaces of designs with a 10G Ethernet interface 8b/10b PCS. It can work with SystemVerilog,Vera, SystemC, E and Verilog HDL environment. XGMII TBI verification IP is developed by experts in Ethernet, who have developed ethernet products in companies like Intel, Cortina-Systems, Emulex, Cisco. We know what it takes to verify a ethenet product.

10G TBI (PCS) Ethernet Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

10G TBI (PCS) Ethernet Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key features

  • Follows 10G specification as defined in IEEE 802.3
  • Supports all types of 8b/10b PCS TX and RX errors insertion/detection.
    • Oversize, undersize, inrange, out of range Packet size errors
    • Missing SPD/EPD/SFD framing errors
    • SPD/SFD on wrong lane
    • CRC Error
    • Lane skew insertion
    • Disparity error injection
    • Invalid /D/ and /K/ character injection
    • Variable preamble and IPG insertion
  • Comes with 8b/10b PCS Tx BFM, 8b/10b PCS Rx BFM, and 8b/10b PCS Monitor
  • Monitor supports detection of all protocol violations.
  • Supports Pause frame generation and detection.
  • Built in coverage analysis.

Block Diagram

Ethernet 10G TBI (PCS) VIP block diagram

Benefits

  • Faster testbench development and more complete verification of 10G 8b/10b designs.
  • Easy to use command interface simplifies testbench control and configuration of 10G 8b/10b TX and RX.
  • Simplifies results analysis.
  • Runs in every major simulation environment.

What’s Included?

  • Complete regression suite (UNH) containing all the testcases.
  • Examples showing how to connect various components, and usage of TXRX BFM and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
Ethernet 10G TBI (PCS) VIP
Vendor
SmartDV Technologies

Provider

SmartDV Technologies
HQ: India
At SmartDV Technologies™, we believe there’s a better way to approach semiconductor intellectual property (IP) for integrated circuits. We’ve been focused exclusively on IP since 2007—so whether you’re sourcing standards-based design IP for your next SoC, ASIC, or FPGA, or seeking verification solutions (VIP) to put your chip design through its paces, you’ll find SmartDV’s IP straightforward to integrate. By combining proprietary SmartCompiler™ technology with the knowledge of hundreds of expert engineers, SmartDV can customize IP to meet your unique design objectives: quickly, economically, and reliably. Don’t allow other suppliers to force onesize-fits-all cores into your chip design. Get the IP you need, tailored to your specifications, with SmartDV: IP Your Way.
Contact SmartDV Technologies

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Frequently asked questions about Single-Protocol PHY IP

What is 10G TBI (PCS) Ethernet Verification IP?

10G TBI (PCS) Ethernet Verification IP is a Single-Protocol PHY IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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