UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT+uHVT periphery h…
- UMC
- 55nm
- ULP
Embedded memory IP cores are fundamental components in modern SoC and ASIC designs, providing fast and efficient on-chip data storage for processors, accelerators, and peripherals.
These IP cores encompass a broad range of volatile and non-volatile memory technologies, including SRAM for high-speed data storage, ROM for fixed program and boot code storage, register files for processor and accelerator architectures, as well as EEPROM, eFuse/OTP, and MTP (Multiple-Time Programmable) memories for configuration data, security credentials, device calibration, and permanent system information.
This catalog allows you to compare embedded memory IP cores from leading vendors based on density, access time, power consumption, and process node compatibility.
Whether you are designing high-performance processors, AI accelerators, automotive systems, or IoT devices, you can find the right embedded memory IP for your design.
UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT+uHVT periphery h…
UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT+uHVT periphery h…
UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT periphery high d…
UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT periphery high d…
UMC 55nm Embedded Flash and Embedded E2PROM Ultra Low Power Split-Gate Process_x005F_x000D_
UMC 55nm Embedded Flash and Embedded E2PROM Ultra Low Power Split-Gate Process
UMC 55nm SST/ulp Logic process standard synchronous high density single port SRAM memory compiler.
UMC 55nm SST/ulp Logic process standard synchronous high density single port SRAM memory compiler.
UMC 55nm eflash/ulp process standard synchronous high density single port SRAM memory compiler.
UMC 55nm eflash/ulp process standard synchronous high density single port SRAM memory compiler.
UMC 55nm SST process standard synchronous high density single port SRAM memory compiler.
UMC 55nm SST process standard synchronous high density single port SRAM memory compiler.
UMC 55nm eflash process , Two Port Register File memory compiler
UMC 55nm eflash process , Two Port Register File memory compiler
UMC 55nm EFLASH Process ULL One Port Register File
UMC 55nm EFLASH Process ULL One Port Register File
UMC 55nm eFlash process process ULL ROM Memory Compiler
UMC 55nm eFlash process process ULL ROM Memory Compiler
55nm eFlash Dual-Port SRAM memory compiler with row redundancy
55nm eFlash Dual-Port SRAM memory compiler with row redundancy
UMC 55nm eFlash eFlash Dual-Port SRAM Memory Compiler
UMC 55nm eFlash eFlash Dual-Port SRAM Memory Compiler
UMC 55nm EFLASH Process Two Port Register File
UMC 55nm EFLASH Process Two Port Register File
UMC 55nm eFlash peocess One Port Register File memory compiler_x005F_x000D_
UMC 55nm eFlash peocess One Port Register File memory compiler
UMC 55nm eFlash Process Dual-Port SRAM with Row redundancy
UMC 55nm eFlash Process Dual-Port SRAM with Row redundancy
UMC 55nm EFLASH Process Dual-Port SRAM Memory Compiler
UMC 55nm EFLASH Process Dual-Port SRAM Memory Compiler
UMC 55nm EFLASH Processy Single-Port SRAM with row repair Memory complier
UMC 55nm EFLASH Processy Single-Port SRAM with row repair Memory complier
UMC 55nm eFlash Single-Port SRAM memory compiler
UMC 55nm eFlash Single-Port SRAM memory compiler
55 SP Dual Port SRAM compiler with 1P4M metal option
55 SP Dual Port SRAM compiler with 1P4M metal option